参数资料
型号: STM8AF51AATBXXXX
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP80
封装: 14 X 14 MM, ROHS COMPLIANT, LQFP-80
文件页数: 8/118页
文件大小: 2173K
代理商: STM8AF51AATBXXXX
STM8AF51xx, STM8AF61xx
Known limitations
Doc ID 14395 Rev 6
105/118
13.2.3
Delay in STOP bit programming leading to reception of supplementary
byte
Description
When receiving one byte in master mode, the STOP bit in the I2C_CR2 register is
programmed just after ADDR bit is cleared in order to generate a STOP condition after the
reception of the byte. If the programming of the STOP bit is delayed after the end of the first
byte reception, the master may receive another byte before the STOP condition is generated
and a wrong data will be received.
Workaround
Mask interrupts while clearing the ADDR bit and programming the STOP bit. As TLI is not
maskable, this software workaround can not be implemented in applications using the TLI
interrupt.
13.2.4
START condition badly generated after misplaced STOP
Description
When the START bit is set in the I2C_CR2 register and a misplaced STOP occurs on the
bus thus leading to a bus error, the START condition on the bus may be badly generated by
the I2C peripheral (glitch on SDA resulting in SDA and SCL tied low simultaneously).
Workaround
When a bus error is detected (through a flag and/or interrupt), check if a START condition
was requested through the I2C_CR2 register. If so, a STOP condition should be generated
followed by a new START condition. This does not avoid the badly generated START
condition, but allows to resynchronize the network on the new START condition.
13.3
USART Interface
Parity error flag (PE) not correctly set when overrun condition occurs
Description
If an overrun condition occurs, the parity error flag (PE) of the UART_SR register is not set
for the frame which caused the overrun condition. The PE flag represents the status of the
last correctly received frame.
Workaround
None.
相关PDF资料
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