参数资料
型号: STM8AF6126TBX
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP32
封装: 7 X 7 MM, ROHS COMPLIANT, LQFP-32
文件页数: 90/99页
文件大小: 881K
代理商: STM8AF6126TBX
Known limitations
STM8AF61xx, STM8AF62xx
Doc ID 14952 Rev 4
13.2
IC interface
13.2.1
Misplaced NACK when receiving 2 bytes in master mode
Description
When receiving two bytes in Master mode the usual sequence is the following:
1.
Set POS and ACK bits of the I2C_CR2 register to ’1’.
2.
Wait for ADDR event (address sent bit in the I2C_CR1 register). When ADDR is set to
‘1’, program ACK to ’0’ and clear ADDR.
3.
Wait for BTF event (byte transfer finished bit in the I2C_CR1 register). When BTF is set
to ‘1’, program the STOP bit to ’1’ in the I2C_CR2 register and read the 2 received
bytes.
The NACK bit may be sent erroneously after the first byte.
Workaround
Use a different software sequence for ADDR and ACK clearing:
1.
Wait for ADDR flag to be set
2.
Mask interrupts
3.
Clear ADDR
4.
Clear ACK bit
5.
Re-enable interrupts
As the TLI is not maskable, this sw workaround can not be applied in an application that
makes use of the TLI.
13.2.2
Data register corrupted
Description
The content of the shift register may be shifted to the left by 1 bit and the second read
operation will return an incorrect value when the following conditions are met:
BTF bit (last data received) set to 1
Software sequence (SET STOP, READ N-1, READ N) delayed (for instance by an
interrupt)
N-1 byte not read before the next SCL rising edge.
Workaround
Mask all active interrupts between the SET STOP and the READ N-1 instruction. As the TLI
is not maskable, this software workaround can not be applied in an application that makes
use of the TLI interrupt.
13.2.3
Delay in STOP bit programming leading to reception of supplementary
byte
Description
When receiving one byte in master mode, the STOP bit in the I2C_CR2 register is
programmed just after ADDR bit is cleared in order to generate a STOP condition after the
reception of the byte. If the programming of the STOP bit is delayed after the end of the first
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