参数资料
型号: STM8AF6126TBY
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP32
封装: 7 X 7 MM, ROHS COMPLIANT, LQFP-32
文件页数: 70/99页
文件大小: 881K
代理商: STM8AF6126TBY
Electrical characteristics
STM8AF61xx, STM8AF62xx
Doc ID 14952 Rev 4
10.3.9
SPI serial peripheral interface
Unless otherwise specified, the parameters given in Table 54 are derived from tests
performed under ambient temperature, fMASTER frequency and VDD supply voltage
conditions. tMASTER = 1/fMASTER.
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (NSS, SCK, MOSI, MISO).
Table 54.
SPI characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
fSCK
1/tc(SCK)
SPI clock frequency
Master mode
0
10
MHz
Slave mode
VDD < 4.5 V
0
6(1)
VDD = 4.5 V to 5.5 V
0
tr(SCK)
tf(SCK)
SPI clock rise and fall time Capacitive load: C = 30 pF
-
25(2)
ns
tsu(NSS)
(3)
NSS setup time
Slave mode
4 * tMASTER
-
th(NSS)
NSS hold time
Slave mode
70
-
tw(SCKH)
tw(SCKL)
SCK high and low time
Master mode,
fMASTER = 8 MHz, fSCK= 4 MHz
110
140
tsu(MI)
tsu(SI)
Data input setup time
Master mode
5
-
Slave mode
5
-
th(MI)
th(SI)
Data input hold time
Master mode
7
-
Slave mode
10
-
ta(SO)
Data output access time
Slave mode
-
3* tMASTER
tdis(SO)
(3)(5) Data output disable time
Slave mode
25
tv(SO)
Data output valid time
Slave mode
(after enable edge)
VDD < 4.5 V
-
75
VDD = 4.5 V to 5.5 V
-
53
tv(MO)
Data output valid time
Master mode (after enable edge)
-
30
th(SO)
Data output hold time
Slave mode (after enable edge)
31
-
Master mode (after enable edge)
12
-
1.
fMAX is fMASTER/2.
2.
The pad has to be configured accordingly (fast mode).
3.
Values based on design simulation and/or characterization results, and not tested in production.
4.
Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
5.
Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.
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