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参数资料
| 型号： | STP1081ABGA-125 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA256 |
| 封装： | PLASTIC, BGA-256 |
| 文件页数： | 3/32页 |
| 文件大小： | 478K |
| 代理商： | STP1081ABGA-125 |
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11
Companion Device for 250/300 MHz UltraSPARC-II Systems
UltraSPARC
-II Data Buffer (UDB-II)
STP1081
Preliminary
July 1997
SIGNAL DESCRIPTIONS
Symbol
Type
Name and Function
EDATA[63:0]
I/O
The UDB-II transfers data over this bus with both the E-Cache SRAMs and the
UltraSPARC-II. On E-Cache misses, this bus is an output, and supplies data to the
E-Cache RAMs from one of its buffers. On E-Cache write backs, data is transferred from
the E-Cache RAMs on this bus into one of the UDB-II microchip buffers. Each of the two
UDB-II microchips handle half the width of the 128-bit data bus from the UltraSPARC-II and
E-Cache. Noncacheable loads and stores transfer data directly between the
Ultra-SPARC-II and the UDB-II data buffers on this bus. For enabling and disabling ECC,
the UDB-II also supports ASI loads and stores from the Ultra-SPARC-II over this bus. This
allows writing or reading of certain control and status registers on the UDB-II for ECC
purposes.
EDPAR[7:0]
I/O
This signal provides eight parity bits for E-Cache data.
SYSDATA[63:0]
I/O
The UDB-II transfers data to the system interconnect over this bus. Data is transferred at
the system interconnect clock rate.
SYSECC[7:0]
I/O
For each write by UltraSPARC-II to the system interconnect, UDB-II generates eight ECC
check bits for each 64-bit piece of data being transferred. The SYSECC bus is then
congured as an output. On input, good ECC check bits generated by slaves are
transferred to the UDB-II over this bus, and checked inside the UDB-II.
CE
O
This pin is driven by the UDB-II to tell the UltraSPARC-II that it has detected a correctable
ECC error on the data that it received from the interconnect (that is, a single-bit error). The
delivery of data to the UltraSPARC-II is stalled until that error is corrected.
UE
O
This pin is driven by the UDB-II to tell the UltraSPARC-II that it has detected an
uncorrectable ECC error on the data that it received from the interconnect.
S_REPLY[3:0]
I
These pins are connected to a unidirectional four-bit bus that receives encoded
acknowledgments from the system controller in response to an address transaction sent
out by UltraSPARC-II.
SYSID[4:0]
I
This bus is used to convey a ve-bit system node ID to the UDB-II from the system
interconnect.
SYSCLK[1:0]
I
This is an input, and has the same frequency as the UPA clock. It is a differential, PECL
clock.
EBUS_CLK[1:0]
I
This is an input from the clock controller, and has the same frequency as the clock for the
processor E-Cache bus. It is a differential, PECL clock pair.
EXT_EVENT
I
This is an input signal used to indicate the clock should be stopped. It is a debug signal
which is set inactive on production systems. This signal powers down the chip when
asserted.
PLL_BYPASS
I
When asserted, this pin causes the phase-lock loop to be bypassed. In that case, the clock
from the differential receiver is passed directly to the clock trunk.
RESET_L
I
This signal is asserted when an external reset request occurs.
CNTL[4:0]
I
UltraSPARC-II uses these signals to request the UDB-II to either load its buffers from the
external cache data bus or to drive the content of its buffers on to this bus.
UDB_H
I
This pin is hardwired to VDD for UDB_H (the UDB-II microchip for the most signicant 72
bits) and to GND for UDB_L (the UDB-II microchip for the least signicant 72 bits).
EPD
I
Indicates that the UltraSPARC–II is in power-down mode.
TDI
I
IEEE standard 1149 test data input. This pin is internally pulled to logic 1 when not driven.
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