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参数资料
| 型号： | STPCC0310BTC3 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 外设及接口 |
| 英文描述： | MULTIFUNCTION PERIPHERAL, PBGA388 |
| 封装： | PLASTIC, BGA-388 |
| 文件页数： | 10/51页 |
| 文件大小： | 836K |
| 代理商： | STPCC0310BTC3 |
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PIN DESCRIPTION
18/51
Release B
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
2.2.7 IDE INTERFACE
PCS1#, PCS3#
Primary Chip Select. These sig-
nals are used as the active high primary master &
slave IDE chip select signals. These signals must
be externally ANDed with the ISAOE# signal be-
fore driving the IDE devices to guarantee it is ac-
tive only when ISA bus is idle.
SCS1#, SCS3#
Secondary Chip Select. These
signals are used as the active high secondary
master & slave IDE chip select signals. These sig-
nals must be externally ANDed with the ISAOE#
signal before driving the IDE devices to guarantee
it is active only when ISA bus is idle.
DA[2:0]
Address. These signals are connected to
DA[2:0] of IDE devices directly or through a buffer.
If the toggling of signals are to be masked during
ISA bus cycles, they can be externally ORed with
ISAOE# before being connected to the IDE devic-
es.
DD[15:0]
Databus. When the IDE bus is active,
they serve as IDE signals DD[11:0]. IDE devices
are connected to SA[19:8] directly and ISA bus is
connected to these pins through two LS245 trans-
ceivers as described in Figure 2.2.
DIORDY
Busy/Ready. This pin serves as IDE sig-
nal DIORDY.
PIRQ
Primary Interrupt Request.
SIRQ
Secondary Interrupt Request.
Interrupt request from IDE channels.
PDRQ
Primary DMA Request.
SDRQ
Secondary DMA Request.
DMA request from IDE channels.
PDACK#
Primary DMA Acknowledge.
SDACK#
Secondary DMA Acknowledge.
DMA acknoledge to IDE channels.
PDIOR#, PDIOW#
Primary I/O Read & Write.
SDIOR#, SDIOW#
Secondary I/O Read & Write.
Primary & Secondary channel read & write.
2.2.8 Monitor Interface
RED, GREEN, BLUE
RGB Video Outputs. These
are the 3 analog color outputs from the RAMDACs
VSYNC
Vertical Synchronisation Pulse. This is
the vertical synchronization signal from the VGA
controller.
HSYNC
Horizontal Synchronisation Pulse. This is
the horizontal synchronization signal from the
VGA controller.
VREF_DAC
DAC Voltage reference. An external
voltage reference is connected to this pin to bias
the DAC.
RSET
Resistor Current Set. This reference cur-
rent input to the RAMDAC is used to set the full-
scale output of the RAMDAC.
COMP
Compensation. This is the RAMDAC com-
pensation pin. Normally, an external capacitor
(typically 10nF) is connected between this pin and
VDD to damp oscillations.
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