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参数资料
| 型号： | STPCC0390BTC3 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 外设及接口 |
| 英文描述： | MULTIFUNCTION PERIPHERAL, PBGA388 |
| 封装： | PLASTIC, BGA-388 |
| 文件页数： | 5/59页 |
| 文件大小： | 932K |
| 代理商： | STPCC0390BTC3 |
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PIN DESCRIPTION
Issue 1.1 - October 16, 2000
13/59
2.2 SIGNAL DESCRIPTIONS
2.2.1 BASIC CLOCKS AND RESETS
SYSRSTI#
System Reset/Power good. This input
is low when the reset switch is depressed. Other-
wise, it reflects the power supply’s power good
signal. This input is asynchronous to all clocks,
and acts as a negative active reset. The reset cir-
cuit initiates a hard reset on the rising edge of this
signal.
SYSRSTO#
Reset Output to System. This is the
system reset signal and is used to reset the rest of
the components (not on Host bus) in the system.
The ISA bus reset is an externally inverted buff-
ered version of this output and the PCI bus reset is
an externally buffered version of this output.
XTALI 14.3MHz Crystal Input
XTALO
14.3MHz Crystal Output. These pins are
connected to the 14.318 MHz crystal to provide
the reference clock for the internal frequency syn-
thesizer to generate all the other clocks.
A 14.318 MHz Series Cut Crystal should be con-
nected between these two pins. Balance capaci-
tors of 15 pF should also be added. In the event of
an external quarzt oscillator providing the master
clock signal to the STPC Consumer-S device, the
TTL signal should be provided on XTALO.
HCLK
Host Clock. This clock supplies the CPU
and the host related blocks. This clock can e dou-
bled inside the CPU and is intended to operate in
the range of 25 to 100 MHz. This clock in generat-
ed internally from a PLL but can be driven directly
from the external system.
DEV_CLK
24MHz Peripheral Clock. This 24MHZ
signal is provided as a convenience for the system
integration of a Floppy Disk driver function in an
external chip.
DCLK
135MHz Dot Clock. This is the Dot clock,
which drives graphics display cycles. Its frequency
can go from 8MHz (using internal PLL) up to 135
MHz, and it is required to have a worst case duty
cycle of 60-40.
This signal is either driven by the internal pll (VGA)
or an external 27MHz oscillator (when the com-
posite video output is enabled). The direction can
be controlled by a strap option or an internal regis-
ter bit.
2.2.2 MEMORY INTERFACE
MCLKI Memory Clock Input. This clock is driving
the SDRAM controller, the graphics engine and
display controller. This input should be a buffered
version of the MCLKO signal with the track lengths
between the buffer and the pin matched with the
track lengths between the buffer and the Memory
Banks.
MCLKO Memory Clock Output. This clock drives
the Memory Banks on board and is generated
from an internal PLL.The default value is 80MHz.
CS#[3:0] Chip Select These signals are used to
disable or enable device operation by masking or
enabling all SDRAM inputs except MCLK, CKE,
and DQM.
BA[0] Memory Bank Address.
MA[10:0]
Memory Address. Multiplexed row and
column address lines.
MD[63:0]
Memory Data. This is the 64-bit memory
data bus. MD[40-0] are read by the device strap
option registers during rising edge of SYSRSTI#.
RAS#[1:0]
Row Address Strobe. These signals
enable row access and precharge. Row address
is latched on rising edge of MCLK when RAS# is
low.
CAS#[1:0]
Column Address Strobe. These sig-
nals enable column access. Column address is
latched on rising edge of MCLK when CAS# is
low.
MWE#
Write Enable. Write enable specifies
whether the memory access is a read (MWE# = H)
or a write (MWE# = L).
DQM#[7:0] Data Mask. Makes data output Hi-Z
after the clock and masks the SDRAM outputs. It
blocks SDRAM data input when DQM active.
2.2.3 PCI INTERFACE
PCI_CLKI 33MHz PCI Input Clock. This signal is
the PCI bus clock input and should be driven from
the PCI_CLKO pin.
PCI_CLKO
33MHz PCI Output Clock. This is the
master PCI bus clock output.
AD[31:0]
PCI Address/Data. This is the 32-bit
multiplexed address and data bus of the PCI. This
bus is driven by the master during the address
phase and data phase of write transactions. It is
driven by the target during data phase of read
transactions. Signals AD[12:11] for internal use
only. Not to be used for External PCI devices.
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