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参数资料
| 型号： | STPCC0390BTC3 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 外设及接口 |
| 英文描述： | MULTIFUNCTION PERIPHERAL, PBGA388 |
| 封装： | PLASTIC, BGA-388 |
| 文件页数： | 8/59页 |
| 文件大小： | 932K |
| 代理商： | STPCC0390BTC3 |
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PIN DESCRIPTION
16/59
Issue 1.1 - October 16, 2000
interrupt controller, so that it may be connected di-
rectly to the IRQ pin of the RTC.
DREQ_MUX[1:0]
ISA Bus Multiplexed DMA Re-
quest. These are the ISA bus DMA request sig-
nals. They are to be encoded before connection to
the
STPC
Consumer-S
using
ISACLK
and
ISACLKX2 as the input selection strobes.
DACK_ENC[2:0] DMA Acknowledge. These are
the ISA bus DMA acknowledge signals. They are
encoded by the STPC Consumer-S before output
and should be decoded externally using ISACLK
and ISACLKX2 as the control strobes.
TC
ISA Terminal Count. This is the terminal count
output of the DMA controller and is connected to
the TC line of the ISA bus. It is asserted during the
last DMA transfer, when the byte count expires.
2.2.5 X-Bus Interface pins
RTCAS#
Real time clock address strobe.This sig-
nal is asserted for any I/O write to port 70H.
RMRTCCS# ROM/Real Time clock chip select.
This signal is asserted if a ROM access is decod-
ed during a memory cycle. It should be combined
with MEMR# or MEMW# signals to properly ac-
cess the ROM. During a IO cycle, this signal is as-
serted if access to the Real Time Clock (RTC) is
decoded. It should be combined with IOR or IOW#
signals to properly access the real time clock.
KBCS# Keyboard Chip Select. This signal is as-
serted if a keyboard access is decoded during a I/
O cycle.
RTCRW# Real Time Clock RW. This pin is a multi-
function pin. When ISAOE# is active, this signal is
used as RTCRW#. This signal is asserted for any
I/O write to port 71H.
RTCDS#
Real Time Clock DS. This pin is a multi-
function pin. When ISAOE# is active, this signal is
used as RTCDS. This signal is asserted for any I/
O read to port 71H.
Note:
RMRTCCS#,
KBCS#,
RTCRW#
and
RTCDS# signals must be ORed externally with
ISAOE# and then connected to the external de-
vice. An LS244 or equivalent function can be used
if OE# is connected to ISAOE# and the output is
provided with a weak pull-up resistor as shown in
Figure 2-2.
2.2.6 LOCAL BUS
PA[21:0]
Address Bus Output.
PD[15:0] Data Bus. This is the 16-bit data bus.
D[7:0] is the LSB and PD[15:8] is the MSB.
PRD#[1:0]
Read Control output. PRD0# is used
to read the LSB and PRD1# to read the MSB.
PWR#[1:0]
Write Control output. PWR0# is used
to write the LSB and PWR1# to write the MSB.
PRDY# Data Ready input. This signal is used to
create wait states on the bus. When HIGH it com-
pletes the cycle without any wait state added.
FCS#[1:0] Flash Chip Select output. These are
the Programmable Chip Select signals for up to 2
banks of Flash memory.
IOCS#[3:0]
I/O Chip Select output. These are the
Programmable Chip Select signals for up to 4 ex-
ternal I/O devices.
2.2.7 IDE INTERFACE
DA[2:0]
Address. These signals are connected to
DA[2:0] of IDE devices directly or through a buffer.
If the toggling of signals are to be masked during
ISA bus cycles, they can be externally ORed with
ISAOE# before being connected to the IDE devic-
es.
DD[15:0]
Databus. When the IDE bus is active,
they serve as IDE signals DD[15:0]. IDE devices
are connected to SA[19:8] directly and ISA bus is
connected to these pins through two LS245 trans-
ceivers as described inFigure 2-2.
PCS1#, PCS3#
Primary Chip Select. These sig-
nals are used as the active high primary master &
slave IDE chip select signals. These signals must
be externally ANDed with the ISAOE# signal be-
fore driving the IDE devices to guarantee it is ac-
tive only when ISA bus is idle.
SCS1#, SCS3# Secondary Chip Select. These
signals are used as the active high secondary
master & slave IDE chip select signals. These sig-
nals must be externally ANDed with the ISAOE#
signal before driving the IDE devices to guarantee
it is active only when ISA bus is idle.
DIORDY
Busy/Ready. This pin serves as IDE sig-
nal DIORDY.
PIRQ
Primary Interrupt Request.
SIRQ
Secondary Interrupt Request.
Interrupt request from IDE channels.
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