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参数资料
| 型号： | STPCC0390BTC3 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 外设及接口 |
| 英文描述： | MULTIFUNCTION PERIPHERAL, PBGA388 |
| 封装： | PLASTIC, BGA-388 |
| 文件页数： | 6/59页 |
| 文件大小： | 932K |
| 代理商： | STPCC0390BTC3 |
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PIN DESCRIPTION
14/59
Issue 1.1 - October 16, 2000
CBE#[3:0] Bus Commands/Byte Enables. These
are the multiplexed command and byte enable
signals of the PCI bus. During the address phase
they define the command and during the data
phase they carry the byte enable information.
These pins are inputs when a PCI master other
than the STPC Consumer-S owns the bus and
outputs when the STPC Consumer-S owns the
bus.
FRAME#
Cycle Frame. This is the frame signal of
the PCI bus. It is an input when a PCI master owns
the bus and is an output when STPC Consumer-S
owns the PCI bus.
IRDY#
Initiator Ready. This is the initiator ready
signal of the PCI bus. It is used as an output when
the STPC Consumer-S initiates a bus cycle on the
PCI bus. It is used as an input during the PCI cy-
cles targeted to the STPC Consumer-S to deter-
mine when the current PCI master is ready to
complete the current transaction.
TRDY# Target Ready. This is the target ready sig-
nal of the PCI bus. It is driven as an output when
the STPC Consumer-S is the target of the current
bus transaction. It is used as an input when STPC
Consumer-S initiates a cycle on the PCI bus.
LOCK#
PCI Lock. This is the lock signal of the PCI
bus and is used to implement the exclusive bus
operations when acting as a PCI target agent.
DEVSEL#
I/O Device Select. This signal is used
as an input when the STPC Consumer-S initiates
a bus cycle on the PCI bus to determine if a PCI
slave device has decoded itself to be the target of
the current transaction. It is asserted as an output
either when the STPC Consumer-S is the target of
the current PCI transaction or when no other de-
vice asserts DEVSEL# prior to the subtractive de-
code phase of the current PCI transaction.
STOP#
Stop Transaction. Stop is used to imple-
ment the disconnect, retry and abort protocol of
the PCI bus. It is used as an input for the bus cy-
cles initiated by the STPC Consumer-S and is
used as an output when a PCI master cycle is tar-
geted to the STPC Consumer-S.
PAR
Parity Signal Transactions. This is the parity
signal of the PCI bus. This signal is used to guar-
antee even parity across AD[31:0], CBE#[3:0],
and PAR. This signal is driven by the master dur-
ing the address phase and data phase of write
transactions. It is driven by the target during data
phase of read transactions. (Its assertion is identi-
cal to that of the AD bus delayed by one PCI clock
cycle)
SERR#
System Error. This is the system error sig-
nal of the PCI bus. It may, if enabled, be asserted
for one PCI clock cycle if target aborts a STPC
Consumer-S initiated PCI transaction. Its asser-
tion by either the STPC Consumer-S or by another
PCI bus agent will trigger the assertion of NMI to
the host CPU. This is an open drain output.
PCI_REQ#[2:0]
PCI Request. This pin are the
three external PCI master request pins. They indi-
cates to the PCI arbiter that the external agents
desire use of the bus.
PCI_GNT#[2:0] PCI Grant. These pins indicate
that the PCI bus has been granted to the master
requesting it on its PCI_REQ#.
PCI_INT[3:0]
PCI Interrupt Request. These are
the PCI bus interrupt signals.
VDD5
5V Power Supply. These power pins are
necessary for 5V ESD protection. In case the PCI
bus is used in 3.45V only, these pins can be con-
nected to 3.45V.
2.2.4 ISA INTERFACE
ISA_CLK, ISA_CLKX2
ISA Clock x1, x2. These
pins generate the Clock signal for the ISA bus and
a Doubled Clock signal. They are also used as the
multiplexor control lines for the Interrupt Controller
Interrupt input lines. ISA_CLK is generated from
either PCICLK/4 or OSC14M/ 2.
OSC14M ISA bus synchronisation clock Output.
This is the buffered 14.318 Mhz clock for the ISA
bus.
LA[23:17] Unlatched Address. When the ISA bus
is active, these pins are ISA Bus unlatched ad-
dress for 16-bit devices. When ISA bus is ac-
cessed by any cycle initiated from PCI bus, these
pins are in output mode. When an ISA bus master
owns the bus, these pins are in input mode.
SA[19:0]
ISA Address Bus. System address bus
of ISA on 8-bit slot. These pins are used as an in-
put when an ISA bus master owns the bus and are
outputs at all other times.
SD[15:0]
I/O Data Bus. These pins are the exter-
nal databus to the ISA bus.
ALE
Address Latch Enable. This is the address
latch enable output of the ISA bus and is asserted
by the STPC Consumer-S to indicate that LA23-
17, SA19-0, AEN and SBHE# signals are valid.
The ALE is driven high during refresh, DMA mas-
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