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参数资料
| 型号： | STR710RZT6 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 66 MHz, RISC MICROCONTROLLER, PQFP144 |
| 封装： | 20 X 20 MM, 0.50 MM PITCH, LQFP-144 |
| 文件页数： | 58/77页 |
| 文件大小： | 1919K |
| 代理商： | STR710RZT6 |
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STR71xF
Electrical parameters
61/77
5.3.8
Communications interfaces
I2C - Inter IC Control Interface
Subject to general operating conditions for V33, fPCLK1, and TA unless otherwise specified.
The STR7 I2C interface meets the requirements of the Standard I2C communication
protocol described in the following table with the restriction mentioned below:
Note:
Restriction: The I/O pins which SDA and SCL are mapped to are not “True” Open-Drain:
when configured as open-drain, the PMOS connected between the I/O pin and V33 is
disabled, but it is still present. Also, there is a protection diode between the I/O pin and V33.
Consequently, when using this I2C in a multi-master network, it is not possible to power off
the STR7X while some another I2C master node remains powered on: otherwise, the
STR7X will be powered by the protection diode.
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (SDA and SCL).
Notes:
1.
Data based on standard I2C protocol requirement, not tested in production.
2.
The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL.
3.
The maximum hold time of the START condition has only to be met if the interface does not stretch the low
Table 34.
I2C Characteristics
Symbol
Parameter
Standard mode
I2C
Fast mode I2C5)
Unit
Min 1)
Max 1)
Min 1)
Max 1)
tw(SCLL)
SCL clock low time
4.7
1.3
s
tw(SCLH)
SCL clock high time
4.0
0.6
tsu(SDA)
SDA setup time
250
100
ns
th(SDA)
SDA data hold time
0 3)
0 2)
900 3)
tr(SDA)
tr(SCL)
SDA and SCL rise time
1000
20+0.1C
b
300
tf(SDA)
tf(SCL)
SDA and SCL fall time
300
20+0.1C
b
300
th(STA)
START condition hold time
4.0
0.6
s
tsu(STA)
Repeated START condition setup
time
4.7
0.6
tsu(STO)
STOP condition setup time
4.0
0.6
s
tw(STO:STA)
STOP to START condition time (bus
free)
4.7
1.3
s
Cb
Capacitive load for each bus line
400
pF
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