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STR91xF
Functional overview
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2.24
A/D converter (ADC)
The STR91xF provides an eight-channel, 10-bit successive approximation analog-to-digital
converter. The ADC input pins are multiplexed with other functions on Port 4 as shown in
Table 3. Following are the major ADC features:
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Fast conversion time, as low as 0.7 usec
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Accuracy. Integral and differential non-linearity are typically within 4 conversion counts.
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0 to 3.6V input range. External reference voltage input pin (AVREF) available on 128-pin
packages for better accuracy on low-voltage inputs. The voltage on AVREF can range
from 1.0V to VDDQ.
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CPU Firmware may convert one ADC input channel at a time, or it has the option to set the
ADC to automatically scan and convert all eight ADC input channels sequentially before
signalling an end-of-conversion
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Automatic continuous conversion mode is available for any number of designated ADC
input channels
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Analog watchdog mode provides automatic monitoring of any ADC input, comparing it
against two programmable voltage threshold values. The ADC unit will set a flag or it will
interrupt the CPU if the input voltage rises above the higher threshold, or drops below the
lower threshold.
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The ADC unit goes to stand-by mode (very low-current consumption) after any reset event.
CPU firmware may also command the ADC unit to stand-by mode at any time.
2.25
Standard timers (TIM) with DMA
The STR91xF has four independent, free-running 16-bit timer/counter modules designated
TIM0, TIM1, TIM2, and TIM3. Each general purpose timer/counter can be configured by
firmware for a variety of tasks including; pulse width and frequency measurement (input
capture), generation of waveforms (output compare and PWM), event counting, delay timing,
and up/down counting.
Each of the four timer units have the following features:
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16-bit free running timer/counter
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Internal timer/counter clock source from a programmable 8-bit prescale of the CCU PCLK
clock output
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Optional external timer/counter clock source from pin P2.4 shared by TIM0/TIM1, and pin
P2.5 shared by TIM2/TIM3. Frequency of these external clocks must be at least 4 times
less the frequency of the internal CCU PCLK clock output. The Master clock (fMSTR) with a
16-bit prescaler can also be selected as an external clock source
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Two dedicated 16-bit Input Capture registers for measuring up to two input signals. Input
Capture has programmable selection of input signal edge detection
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Two dedicated 16-bit Output Compare registers for generation up to two output signals
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PWM output generation with 16-bit resolution of both pulse width and frequency
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One pulse generation in response to an external event
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A dedicated interrupt to the CPU with five interrupt flags