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参数资料
| 型号： | STR912FW42X6 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 96 MHz, RISC MICROCONTROLLER, PQFP128 |
| 封装： | 14 X 14 MM, PLASTIC, LQFP-128 |
| 文件页数： | 67/73页 |
| 文件大小： | 1538K |
| 代理商： | STR912FW42X6 |
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STR91xF
Functional overview
7/73
2
Functional overview
2.1
System-in-a-Package (SiP)
The STR91xF is a SiP device, comprised of two stacked die. One die is the ARM966E-S CPU
with peripheral interfaces and analog functions, and the other die is the burst Flash. The two die
are connected to each other by a custom high-speed 32-bit burst memory interface and a serial
JTAG test/programming interface.
2.2
Package choice
STR91xF devices are available in 128-pin (14 x 14 mm) and 80-pin (12 x 12 mm) LQFP
packages. Refer to the Table 1 on page 6 and to Table 31 on page 70 for a list of available
peripherals for each of the package choices.
2.3
ARM966E-S CPU core
The ARM966E-S core inherently has separate instruction and data memory interfaces (Harvard
architecture), allowing the CPU to simultaneously fetch an instruction, and read or write a data
item through two Tightly-Coupled Memory (TCM) interfaces as shown in Figure 1. The result is
streamlined CPU Load and Store operations and a significant reduction in cycle count per
instruction. In addition to this, a 5-stage pipeline is used to increase the amount of operational
parallelism, giving the most performance out of each clock cycle.
Ten DSP-enhanced instruction extensions are supported by this core, including single-cycle
execution of 32x16 Multiply-Accumulate, saturating addition/subtraction, and count leading-
zeros.
The ARM966E-S core is binary compatible with 32-bit ARM7 code and 16-bit Thumb code.
2.4
Burst Flash memory interface
A Burst Flash memory interface (Figure 1) has been integrated into the Instruction TCM
(I-TCM) path of the ARM966E-S core. Also in this path is a 4-instruction Pre-Fetch Queue
(PFQ) and a 4-entry Branch Cache (BC), enabling the ARM966E-S core to perform up to 96
MIPS while executing code directly from Flash memory. This architecture provides high
performance levels without a costly instruction SRAM, instruction cache, or external SDRAM.
Eliminating the instruction cache also means interrupt latency is reduced and code execution
becomes more deterministic.
2.4.1
Pre-Fetch Queue (PFQ)
As the CPU core accesses sequential instructions through the I-TCM, the PFQ always looks
ahead and will pre-fetch instructions, taking advantage any idle bus cycles due to variable
length instructions. The PFQ will fetch 32-bits at a time from the Burst Flash memory at a rate
of up to 96 MHz.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| STR912FW42X6 | 制造商:STMicroelectronics 功能描述:256K Flash 96K sram Ethernet USB CAN |
| STR912FW42X6T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:ARM966E-S TM 16/32-Bit Flash MCU with Ethernet, USB, CAN, AC motor control, 4 timers, ADC, RTC, DMA |
| STR912FW44X6 | 功能描述:ARM微控制器 - MCU TQFP 128 14x14x1.4 1 RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 处理器系列:STM32F373xx 数据总线宽度:32 bit 最大时钟频率:72 MHz 程序存储器大小:256 KB 数据 RAM 大小:32 KB 片上 ADC:Yes 工作电源电压:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作温度范围:- 40 C to + 85 C 封装 / 箱体:LQFP-48 安装风格:SMD/SMT |
| STR912FW44X6 | 制造商:STMicroelectronics 功能描述:512K Flash 96K sram Ethernet USB CAN |
| STR912FW44X6T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:ARM966E-S TM 16/32-Bit Flash MCU with Ethernet, USB, CAN, AC motor control, 4 timers, ADC, RTC, DMA |
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