参数资料
型号: SX8723CWLTDT
厂商: Semtech
文件页数: 13/67页
文件大小: 0K
描述: IC DAS ADC 16BIT I2C/SRL
标准包装: 1
系列: ZoomingADC™
类型: 数据采集系统(DAS)
输入类型: 差分
输出类型: 数字
接口: I²C
安装类型: 表面贴装
封装/外壳: 12-WFDFN 裸露焊盘
供应商设备封装: 12-MLPD-EP(4x4)
包装: 标准包装
其它名称: SX8723CWLTDTDKR
www.semtech.com/products/
Page 20
ADVANCED COMMUNICATIONS & SENSING
DATASHEET
SX8723C
ZoomingADC for sensing data acquisition
Revision 1.01
January 2011
Semtech
7.1.3 PGA & ADC Enabling
Depending on the application objectives, the user may enable or bypass each PGA stage. This is done according to the
word Enable and the coding given in Table 7. To reduce power dissipation, the ADC can also be inactivated while idle.
7.2 ZoomingADC Registers
The system has a bank of eight 8-bit registers: six registers are used to configure the acquisition chain (RegAcCfg0 to
RegAcCfg5), and two registers are used to store the output code of the analog-to-digital conversion (RegAcOutMsb &
Lsb).
(r = read; w = write; rw = read & write)
(1)
Out: (r) digital output code of the analog-to-digital converter. (MSB = Out[15])
(2)
Start: (w) setting this bit triggers a single conversion (after the current one is finished). This bit always reads back 0.
Table 7. ADC and PGA Enabling
Enable
(RegACCfg1[3:0])
Block
XXX0
XXX1
ADC disabled
ADC enabled
XX0X
XX1X
PGA1 disabled
PGA1 enabled
X0XX
X1XX
PGA2 disabled
PGA2 enabled
0XXX
1XXX
PGA3 disabled
PGA3 enabled
Table 8.
Periferal Registers to Configure the Acquisition Chain (AC) and to Store the Analog-to-Digital
Conversion (ADC) Result
Register Name
Bit position
76
543210
RegACOutLsb
Out[7:0]
RegACOutMsb
Out[15:8]
RegACCfg0
Default values:
Start
SetNelconv
01, Note 3
SetOsr
010, Note 4
Continuous
-
RegACCfg1
Default value:
IbAmpAdc
11, Note 7
IbAmpPga
11, Note 8
Enable
0000, Note 9
RegACCfg2
Default value:
SetFs
Pga2Gain
Pga2Offset
0000, Note 14
RegACCfg3
Default value:
Pga1Gain
Pga3Gain
0001100, Note 13
RegACCfg4
Default value:
-
0
Pga3Offset
0000000, Note 15
RegACCfg5
Default value:
Busy
Def
Amux
00000, Note 18
Vmux
Not
Recommended
for
Designs
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