参数资料
型号: SX8725CWLTDT
元件分类: ADC
英文描述: 2-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL/PARALLEL ACCESS, PDSO12
封装: 4 X 4 MM, HALOGEN FREE AND ROHS COMPLIANT, MLPD-12
文件页数: 66/68页
文件大小: 1718K
代理商: SX8725CWLTDT
www.semtech.com/products/
Page 7
ADVANCED COMMUNICATIONS & SENSING
DATASHEET
SX8725C
ZoomingADC for sensing data acquisition
Revision 1.01
January 2011
Semtech
(1)
Gain defined as overall PGA gain GDTOT = GD1 x GD2 x GD3. Maximum input voltage is given by: VIN,MAX =
±(VREF / 2) (OSR / OSR+1).
(2)
Offset due to tolerance on GDoff2 or GDoff3 setting. For small intrinsic offset, use only ADC and PGA1.
(3)
Measured with block connected to inputs through Amux block. Normalized input sampling frequency for input impedance is fS = 500 kHz
(fS max, worst case). This figure must be multiplied by 2 for fS = 250 kHz, 4 for fS = 125 kHz. Input impedance is proportional to 1/fS.
(4)
Figure independent from gain and sampling frequency. fS. The effective output noise is reduced by the over-sampling ratio
(5)
Resolution is given by n = 2 log2(OSR) + log2(NELCONV). OSR can be set between 8 and 1024, in powers of 2. NELCONV can be set to 1, 2, 4 or 8.
(6)
If a ramp signal is applied to the input, all digital codes appear in the resulting ADC output data.
(7)
Gain error is defined as the amount of deviation between the ideal (theoretical) transfer function and the measured transfer function
(with the offset error removed).
(8)
Offset error is defined as the output code error for a zero volt input (ideally, output code = 0). For 1 LSB offset, NELCONV must be at least 2.
(9)
INL defined as the deviation of the DC transfer curve of each individual code from the best-fit straight line. This specification holds over
the full scale.
(10)
DNL is defined as the difference (in LSB) between the ideal (1 LSB) and measured code transitions for successive codes.
(11)
Values for Gain = 1. PSRR is defined as the amount of change in the ADC output value as the power supply voltage changes.
ADC STATIC PERFORMANCES
Resolution
(No Missing Codes)
n
616
Bits
Gain Error
±0.15
%
Offset Error
n = 16 bits. Note 8
±1LSB
Integral Non-Linearity
INL
resolution n = 12 bits. Note 9
±0.6
LSB
resolution n = 16 bits. Note 9
±1.5
LSB
Differential Non-Linearity
DNL
resolution n = 12 bits. Note 10
±0.5
LSB
resolution n = 16 bits. Note 10
±0.5
LSB
Power Supply Rejection Ratio
DC
PSRR
VBATT = 5V +/- 0.3V. Note 11
78
dB
VBATT = 3V +/- 0.3V. Note 11
72
dB
ADC DYNAMIC PERFORMANCES
Conversion Time
TCONV
n = 12 bits. Note 12
133
fs cycles
n = 16 bits. Note 12
517
fs cycles
Throughput Rate (Continuous Mode)
1/TCONV
n = 12 bits, fs = 250 kHz
1.88
kSps
n = 16 bits, fs = 250 kHz
0.483
kSps
PGA Stabilization Delay
OSR
fs cycles
ZADC ANALOG QUIESCENT CURRENT
ADC Only Consumption
IQ
VBATT = 5.5V/3.3V
285/210
μA
PGA1 Consumption
VBATT = 5.5V/3.3V
104/80
μA
PGA2 Consumption
VBATT = 5.5V/3.3V
67/59
μA
PGA3 Consumption
VBATT = 5.5V/3.3V
98/91
μA
ANALOG POWER DISSIPATION : All PGAs & ADC Active
Normal Power Mode
VBATT = 5.5V/3.3V. Note 14
4.0/2.0
mW
3/4 Power Reduction Mode
VBATT = 5.5V/3.3V. Note 15
3.2/1.6
mW
1/2 Power Reduction Mode
VBATT = 5.5V/3.3V. Note 16
2.4/1.1
mW
1/4 Power Reduction Mode
VBATT = 5.5V/3.3V. Note 17
1.5/0.7
mW
Table 4.
ZoomingADC Specifications
Parameter
Symbol
Condition
Min
Typ
Max
Unit
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