参数资料
型号: SY10E136JZTR
厂商: Micrel Inc
文件页数: 8/9页
文件大小: 0K
描述: IC COUNTER U/D 6BIT UNIV 28-PLCC
标准包装: 750
系列: 10E
逻辑类型: 二进制计数器
方向: 上,下
元件数: 1
每个元件的位元数: 6
复位: 异步
计时: 同步
计数速率: 650MHz
触发器类型: 正边沿
电源电压: 4.2 V ~ 5.5 V
工作温度: 0°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-LCC(J 形引线)
供应商设备封装: 28-PLCC
包装: 带卷 (TR)
其它名称: SY10E136JZ TR
8
SY10E136
SY100E136
Micrel, Inc.
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
Figure 4. Programmable Divider Waveforms
Figure 5. 24-bit Programmable Divider Architecture
The exercise of building a programmable divider then
becomes simply determining what value to load into the
counter to accomplish the desired division. Since the load
operation requires a clock pulse, to divide by N, N-1 must
be loaded into the counter. A single E136 device is capable
of divide ratios of 2 to 64, inclusive. Table 1 outlines the
load values for the various divide ratios. Figure 4 presents
the waveforms resulting from a divide by 37 operation. Note
that the availability of the COUT complimentary output (COUT)
allows the user to choose the polarity of the divide by output.
For single device programmable counters, the E016
counter is probably a better choice than the E136.
The
E016 has an internal feedback to control the reloading of
the counter. This not only simplifies board design, but also
will result in a faster maximum count frequency.
For programmable dividers of larger than 8 bits, the
benefits of the E016 diminishes and, in fact, for very wide
dividers, the E136 will provide the capability of a faster
count frequency. Figure 5 shows the architecture of a 24-
bit programmable divider implemented using E136 counters.
Note the need for one external gate to control the loading of
the entire counter chain. An ideal device for the external
gating of this architecture would be the 4-input OR function
in the 8-lead SOIC ECLinPS Lite family. However, the
final decision as to what device to use for external gating
requires a balancing of performance needs, cost and
available board space. Note that because of the need for
external gating, the maximum count frequency of a given
sized programmable divider will be less than that of a single
cascaded counter.
CLOCK
COUT
S1
LOAD
100100
100011
000011
000010
000001
000000
LOAD
DIVIDE BY 37
CLK
CIN
CLIN
CLOCK
"LO"
LSB
Q0 – Q5
D0 – D5
"LO"
Q0 – Q5
D0 – D5
Q0 – Q5
D0 – D5
MSB
Q0 – Q5
D0 – D5
S1
CLK
S1
COUT
CLOUT
CIN
CLIN
COUT
CLOUT
CIN
CLIN
COUT
CLOUT
CIN
CLIN
COUT
CLOUT
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