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参数资料
| 型号： | SYS8512RKX-12 |
| 元件分类： | SRAM |
| 英文描述： | 512K X 8 MULTI DEVICE SRAM MODULE, 120 ns, PSMA36 |
| 封装： | PLASTIC, MODULE, SIP-36 |
| 文件页数： | 6/7页 |
| 文件大小： | 471K |
| 代理商： | SYS8512RKX-12 |
SYS8512RKX-70/85/10/12
ISSUE 1.0 March 1999
6
Write Cycle No.2 Timing Waveform
CW (2)
WR (4)
WC
AS (3)
DW
DH
OH
OW
WHZ(5)
AW
WP (1)
Don't
t
Address
CS
WE
Dout
Din
t
Care
High-Z
(7)
(8)
AC Characteristics Notes
(1) A write occurs during the overlap (t
WP) of a low CS and a low WE.
(2) t
CW is measured from the earlier of CS or WE going high to the end of write cycle.
(3) t
AS is measured from the address valid to the beginning of write.
(4) t
WR is measured from the earliest of CS or WE going high to the end of write.
(5) During this period, I/O pins are in the output state. Input signals out of phase must not be applied.
(6) If CS goes low simultaneously with WE going low or after WE going low , outputs remain in a high impedance
state.
(7) D
OUT is in the same phase as written data of this write cycle.
(8) D
OUT is the read data of next address.
(9) If CS is low during this period, I/O pins are in the output state, and inputs out of phase must not be applied to I/
O pins.
(10) This parameter is sampled and not 100% tested.
(11) t
WHZ is defined as the time at which the outputs achieve open circuit conditions and is not referenced to output voltage
levels. This parameter is sampled and not 100% tested.
t R
tCDR
4.5V
2.2V
4.5V
2.2V
0V
DATA RETENTION MODE
Vcc
CS
V DR
CS > Vcc -0.2V
Data Retention Waveform
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相关代理商/技术参数 |
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|---|---|
| SYS8512RKX-70 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x8 SRAM Module |
| SYS8512RKX-85 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x8 SRAM Module |
| SYS8512RKXI-10 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x8 SRAM Module |
| SYS8512RKXI-12 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x8 SRAM Module |
| SYS8512RKXI-70 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x8 SRAM Module |
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