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参数资料
| 型号： | T436416A |
| 厂商： | TM Technology, Inc. |
| 英文描述： | 4M X 16 SDRAM |
| 中文描述： | 4米× 16内存 |
| 文件页数： | 12/29页 |
| 文件大小： | 712K |
| 代理商： | T436416A |
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TE
CH
tm
SIMPLIFIED TRUTH TABLE
T436416A
TM Technology Inc. reserves the right
P.12
to change products or specifications without notice.
Publication Date: MAY. 2003
Revision: B
COMMAND
CKEn-1 CKEn
CS
RAS
CAS
WE DQM 0,1 A
10
/AP A
9
~A
0,
X
A11
Note
Register
Mode Register Set
Auto Refresh
H
X
H
L
L
L
L
X
1,2
Entry
H
L
L
L
L
H
X
X
3
L
H
L
H
X
L
H
X
H
H
X
H
Refresh
Self
Refresh
Exit
L
H
X
X
3
Bank Active & Row Address
H
X
X
V
Row Address
Auto Precharge Disable
Auto Precharge Enable
L
H
L
H
Read Column
Address
Write & Column
Address
Burst Stop
H
X
L
H
L
H
X
V
Column
Address
(A0~A7)
Column
Address
(A0~A7)
4,5
Auto Precharge Disable
Auto Precharge Enable
H
X
L
H
L
L
X
V
4,5
H
X
L
H
H
L
X
X
6
Bank Selection
Both Banks
V
X
L
H
Precharge
H
X
L
L
H
L
X
4
H
L
X
H
L
H
L
X
V
X
X
H
X
V
X
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
H
L
X
Clock Suspend or
Active Power Down
Exit
Entry
L
H
X
X
H
L
X
Precharge Power Down
Mode
Exit
L
H
X
X
DQM
H
V
X
7
H
H
H
L
X
H
X
H
X
H
No Operation Command
X
X
X
(V=Valid , X=Don’t Care , H=Logic High , L=logic Low)
Notes :
1. OP Code : Operation Code. A
0
~A
11
, BA0~BA1 : Program keys.(@MRS)
2. MRS can be issued only at both banks precharge state. A new command can be issued after 2 clock cycle of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row
precharge command is meant by ‘Auto’. Auto / self refresh can be issued only at both banks precharge state.
4. BA0~BA1 : Bank select address.
If both BA0 and BA1 are ’Low’ : at read , write , row active and precharge , bank A is selected.
If both BA0 is ‘Low’ and BA1 is ‘High’ : at read , write , row active and precharge , bank B is selected.
If both BA0 is ‘High’ and BA1 is ‘Low’ : at read , write , row active and precharge , bank C is selected.
If both BA0 and BA1 are ’High’ : at read , write , row active and precharge , bank D is selected
If A
10
/AP is ‘High’ : at row precharge , BA0 and BA1 ignored and all banks are selected.
5. During burst read or write with auto precharge , new read/write command cannotbeissued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at
t
RP
after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
相关PDF资料 |
PDF描述 |
|---|---|
| T436416A-10S | 4M X 16 SDRAM |
| T436416A-10SG | Terminal Block End Barrier; For Use With:AB1 Series Terminal Blocks; Accessory Type:End Barrier; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes |
| T436416A-6S | 4M X 16 SDRAM |
| T436416A-6SG | 4M X 16 SDRAM |
| T436416A-7.5S | 4M X 16 SDRAM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| T436416A-10S | 制造商:TMT 制造商全称:TMT 功能描述:4M X 16 SDRAM |
| T436416A-10SG | 制造商:TMT 制造商全称:TMT 功能描述:4M X 16 SDRAM |
| T436416A-6S | 制造商:TMT 制造商全称:TMT 功能描述:4M X 16 SDRAM |
| T436416A-6SG | 制造商:TMT 制造商全称:TMT 功能描述:4M X 16 SDRAM |
| T436416A-7.5S | 制造商:TMT 制造商全称:TMT 功能描述:4M X 16 SDRAM |
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