参数资料
| 型号： | T89C5115-TDSIM |
| 厂商： | Atmel |
| 文件页数： | 16/113页 |
| 文件大小： | 0K |
| 描述： | IC 8051 MCU FLASH 16K 24SOIC |
| 标准包装： | 31 |
| 系列： | 89C |
| 核心处理器： | 8051 |
| 芯体尺寸： | 8-位 |
| 速度： | 40MHz |
| 连通性： | UART/USART |
| 外围设备： | POR，PWM，WDT |
| 输入/输出数： | 20 |
| 程序存储器容量： | 16KB（16K x 8） |
| 程序存储器类型： | 闪存 |
| EEPROM 大小： | 2K x 8 |
| RAM 容量： | 512 x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 3 V ~ 5.5 V |
| 数据转换器： | A/D 8x10b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 24-SOIC（0.295"，7.50mm 宽） |
| 包装： | 管件 |
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dsPIC33FJ12MC201/202
DS70265E-page 112
2007-2011 Microchip Technology Inc.
8.2
Clock Switching Operation
Applications are free to switch among any of the four
clock sources (Primary, LP, FRC, and LPRC) under
software control at any time. To limit the possible side
effects of this flexibility, dsPIC33FJ12MC201/202
devices have a safeguard lock built into the switch
process.
8.2.1
ENABLING CLOCK SWITCHING
To enable clock switching, the FCKSM1 Configuration
bit in the Configuration register must be programmed to
‘0’. (Refer to Section 21.1 “Configuration Bits” for
further details.) If the FCKSM1 Configuration bit is
unprogrammed (‘1’), the clock switching function and
Fail-Safe Clock Monitor function are disabled. This is
the default setting.
The NOSC control bits (OSCCON<10:8>) do not
control the clock selection when clock switching is
disabled. However, the COSC bits (OSCCON<14:12>)
reflect the clock source selected by the FNOSC
Configuration bits.
The OSWEN control bit (OSCCON<0>) has no effect
when clock switching is disabled. It is held at ‘0’ at all
times.
8.2.2
OSCILLATOR SWITCHING SEQUENCE
Performing a clock switch requires this basic
sequence:
1.
If
desired,
read
the
COSC
bits
(OSCCON<14:12>) to determine the current
oscillator source.
2.
Perform the unlock sequence to allow a write to
the OSCCON register high byte.
3.
Write the appropriate value to the NOSC control
bits (OSCCON<10:8>) for the new oscillator
source.
4.
Perform the unlock sequence to allow a write to
the OSCCON register low byte.
5.
Set the OSWEN bit (OSCCON<0>) to initiate
the oscillator switch.
Once the basic sequence is completed, the system
clock hardware responds automatically as follows:
1.
The clock switching hardware compares the
COSC status bits with the new value of the
NOSC control bits. If they are the same, the
clock switch is a redundant operation. In this
case, the OSWEN bit is cleared automatically
and the clock switch is aborted.
2.
If a valid clock switch has been initiated, the
LOCK
(OSCCON<5>)
and
the
CF
(OSCCON<3>) status bits are cleared.
3.
The new oscillator is turned on by the hardware
if it is not currently running. If a crystal oscillator
must be turned on, the hardware waits until the
Oscillator Start-up Timer (OST) expires. If the
new source is using the PLL, the hardware waits
until a PLL lock is detected (LOCK = 1).
4.
The hardware waits for 10 clock cycles from the
new clock source and then performs the clock
switch.
5.
The hardware clears the OSWEN bit to indicate a
successful clock transition. In addition, the NOSC
bit values are transferred to the COSC status bits.
6.
The old clock source is turned off at this time,
with the exception of LPRC (if WDT or FSCM
are enabled) or LP (if LPOSCEN remains set).
8.3
Fail-Safe Clock Monitor (FSCM)
The Fail-Safe Clock Monitor allows the device to
continue to operate even in the event of an oscillator
failure. The FSCM function is enabled by programming.
If the FSCM function is enabled, the LPRC internal
oscillator runs at all times (except during Sleep mode)
and is not subject to control by the Watchdog Timer.
In the event of an oscillator failure, the FSCM
generates a clock failure trap event and switches the
system clock over to the FRC oscillator. Then the
application program can either attempt to restart the
oscillator or execute a controlled shutdown. The trap
can be treated as a warm Reset by simply loading the
Reset address into the oscillator fail trap vector.
If the PLL multiplier is used to scale the system clock,
the internal FRC is also multiplied by the same factor
on clock failure. Essentially, the device switches to
FRC with PLL on a clock failure.
Note:
Primary Oscillator mode has three different
submodes (XT, HS, and EC), which are
determined by the POSCMD<1:0> Config-
uration bits. While an application can
switch to and from Primary Oscillator
mode in software, it cannot switch among
the different primary submodes without
reprogramming the device.
Note 1:
The processor continues to execute code
throughout the clock switching sequence.
Timing-sensitive code should not be
executed during this time.
2:
Direct clock switches between any pri-
mary oscillator mode with PLL and
FRCPLL mode are not permitted. This
applies to clock switches in either direc-
tion. In these instances, the application
must switch to FRC mode as a transition
clock source between the two PLL modes.
3:
Refer
to
Section
7.
“Oscillator”
(DS70186) in the “dsPIC33F/PIC24H
Family Reference Manual”
for details.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| T89C5115-TISIM | 功能描述:IC 8051 MCU FLASH 16K 28SOIC RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微控制器， 系列:89C 标准包装:9 系列:87C 核心处理器:8051 芯体尺寸:8-位 速度:40/20MHz 连通性:UART/USART 外围设备:POR，WDT 输入/输出数:32 程序存储器容量:32KB（32K x 8） 程序存储器类型:OTP EEPROM 大小:- RAM 容量:256 x 8 电压 - 电源 (Vcc/Vdd):4.5 V ~ 5.5 V 数据转换器:- 振荡器型:内部 工作温度:0°C ~ 70°C 封装/外壳:40-DIP（0.600"，15.24mm） 包装:管件 |
| T89C5115-TISUM | 功能描述:IC 8051 MCU FLASH 16K 28SOIC RoHS:是 类别:集成电路 (IC) >> 嵌入式 - 微控制器， 系列:89C 标准包装:1,500 系列:AVR® ATtiny 核心处理器:AVR 芯体尺寸:8-位 速度:16MHz 连通性:I²C，LIN，SPI，UART/USART，USI 外围设备:欠压检测/复位，POR，PWM，温度传感器，WDT 输入/输出数:16 程序存储器容量:8KB（4K x 16） 程序存储器类型:闪存 EEPROM 大小:512 x 8 RAM 容量:512 x 8 电压 - 电源 (Vcc/Vdd):2.7 V ~ 5.5 V 数据转换器:A/D 11x10b 振荡器型:内部 工作温度:-40°C ~ 125°C 封装/外壳:20-SOIC（0.295"，7.50mm 宽） 包装:带卷 (TR) |
| T89C5121 | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:8-bit Microcontroller with MULTI-PROTOCOL SMART CARD INTERFACE |
| T89C5121-ICRIL | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:8-bit Microcontroller with MULTI-PROTOCOL SMART CARD INTERFACE |
| T89C5121-ICSIL | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:8-bit Microcontroller with Multi protocol SMART Card Interface |
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