参数资料
型号: T89C5115-TDSIM
厂商: Atmel
文件页数: 81/113页
文件大小: 0K
描述: IC 8051 MCU FLASH 16K 24SOIC
标准包装: 31
系列: 89C
核心处理器: 8051
芯体尺寸: 8-位
速度: 40MHz
连通性: UART/USART
外围设备: POR,PWM,WDT
输入/输出数: 20
程序存储器容量: 16KB(16K x 8)
程序存储器类型: 闪存
EEPROM 大小: 2K x 8
RAM 容量: 512 x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 5.5 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 24-SOIC(0.295",7.50mm 宽)
包装: 管件
7
AT89C5115
4128G–8051–02/08
I/O Configurations
Each Port SFR operates via type-D latches, as illustrated in Figure 1 for Ports 3 and 4. A
CPU ’write to latch’ signal initiates transfer of internal bus data into the type-D latch. A
CPU ’read latch’ signal transfers the latched Q output onto the internal bus. Similarly, a
’read pin’ signal transfers the logical level of the Port pin. Some Port data instructions
activate the ’read latch’ signal while others activate the ’read pin’ signal. Latch instruc-
tions are referred to as Read-Modify-Write instructions. Each I/O line may be
independently programmed as input or output.
Port Structure
Figure 1 shows the structure of Ports, which have internal pull-ups. An external source
can pull the pin low. Each Port pin can be configured either for general-purpose I/O or
for its alternate input output function.
To use a pin for general-purpose output, set or clear the corresponding bit in the Px reg-
ister (x = 1 to 4). To use a pin for general-purpose input, set the bit in the Px register.
This turns off the output FET drive.
To configure a pin for its alternate function, set the bit in the Px register. When the latch
is set, the ’alternate output function’ signal controls the output level (See Figure 1). The
operation of Ports is discussed further in ’Quasi-Bi-directional Port Operation’
paragraph.
Figure 1. Ports Structure
Note:
1. The internal pull-up can be disabled on P1 when analog function is selected.
D
CL
Q
LATCH
INTERNAL
WRITE
TO
LATCH
READ
PIN
READ
LATCH
ALTERNATE
OUTPUT
FUNCTION
VCC
INTERNAL
PULL-UP (1)
ALTERNATE
INPUT
FUNCTION
BUS
P2.x
P3.x
P4.x
P1.x
(1)
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