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参数资料
| 型号： | TAPC640 |
| 厂商： | Lineage Power |
| 英文描述： | High-Speed Switching ATM Port Controller (APC)(高速开关ATM端口控制器) |
| 中文描述： | 高速开关ATM端口控制器（APC）（高速开关自动柜员机端口控制器） |
| 文件页数： | 4/8页 |
| 文件大小： | 165K |
| 代理商： | TAPC640 |
TAPC640
High-Speed Switching ATM Port Controller (APC)
Product Brief
August 2000
4
Lucent Technologies Inc.
Description
(continued)
UTOPIA Interface (UPI)
The UPI controls the transfer of ATM cells between the
APC and multiple physical layer devices (MPHYs) con-
nected to it, via two full-duplex UTOPIA Level II com-
patible interfaces operating independently at up to
52 MHz.
The UPI supports linear aggregation of ATM traffic up
to 622 Mbits/s. Each UTOPIA interface can be enabled
independently and is always a bus master. Receive
parity checking can be enabled or disabled. Transmit
parity generation can be configured as odd or even.
Each transmit interface can be configured to internally
loopback cells to its receive interface independently for
diagnostic purposes.
Additionally, the UPI can support an extended cell for-
mat and an external port inverse multiplexer (PIMUX)
device to interface with link rates greater than
622 Mbits/s such as OC-48 trunks.
Each interface can be independently configured to
operate in 16-bit or 8-bit mode (for UTOPIA Level 1
compatibility), with a standard or extended cell format
and its own contiguous UTOPIA poll address range to
support up to 31 MPHY devices
*
.
For special cells (OA&M and RM), the UPI also checks
(on receive) and inserts (on transmit) the payload CRC-
10 field.
Header Look-Up and Control Memory Inter-
face (HLX)
The HLX performs a three-level ingress look-up and
one-level egress look-up in external memory to fetch
connection information for up to 64K ingress and
egress connections. The HLX supports MPHY port
configuration (UNI or NNI), VP or VC switching, ATM
header validation, ingress cell capture and cell recogni-
tion (e.g., RM and OA&M cells).
Additionally, the HLX accesses control memory tables
maintained in external synchronous static memory,
SSRAM (CRAM), to support queuing, scheduling
(QSC), and OA&M (NMXSOX) operations.
Virtual Connection Table Memory Interface
(VCT)
The VCT handles all the necessary operations needed
to read, write, and refresh the ingress and egress vir-
tual connection parameter tables, maintained in exter-
nal SDRAM (VCRAM) for up to 64K connections.
Policing Generic Cell Rate (GCR)
The GCR
implements two instances of the generic cell
rate algorithm (GCRA) for each connection to police
cells for conformance to their negotiated traffic con-
tracts. It uses the virtual scheduling algorithm outlined
in ITU-T I.371 to determine conformance. Seven possi-
ble policing configurations are supported for each
GCRA instance including all the conformance defini-
tions specified in ATM Forum Traffic Management
Specification Version 4.0.
Policing can be enabled or disabled on a per-connec-
tion basis, or globally enabled or disabled. The policing
action, monitor, tag, or drop can be programmed sepa-
rately for each individual leaky bucket on a per-connec-
tion basis. The range of policed rates goes from
424 bits/s (one cell per second) to the maximum sup-
ported rate of 622 Mbits/s.
Buffer Management Controller (BMX)
The GCRBMX block performs buffer management
functions, by checking a variety of per-connection, per-
port, and per-traffic class thresholds. They are used to
drop a cell before it is queued.
A CLP0+1 discard threshold, an optional CLP1 discard
threshold, and an optional early packet discard (EPD)
threshold are provided for each connection on ingress
and egress. These thresholds can be configured as
static or dynamic.
The dynamic threshold is based on an effective buffer
allocation for the connection. This allocation is not used
directly as the discard threshold. The overall reserve
and specific congestion conditions add to or subtract
from the buffer allocation to continuously adjust the
threshold. These adjustments are based on the avail-
able reserve of the common buffer pool and the con-
gestion threshold established for the traffic class to
which the connection belongs. This balances the
losses of the given circuit against the overall state of
the system. A guaranteed minimum buffer space is
supported during periods of heavy buffer use.
* Only 31 MPHY devices can be supported over the two UTOPIA in-
terfaces combined.
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相关代理商/技术参数 |
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