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参数资料
| 型号： | TAPC640 |
| 厂商： | Lineage Power |
| 英文描述： | High-Speed Switching ATM Port Controller (APC)(高速开关ATM端口控制器) |
| 中文描述： | 高速开关ATM端口控制器（APC）（高速开关自动柜员机端口控制器） |
| 文件页数： | 7/8页 |
| 文件大小： | 165K |
| 代理商： | TAPC640 |
Product Brief
August 2000
TAPC640
High-Speed Switching ATM Port Controller (APC)
7
Lucent Technologies Inc.
Description
(continued)
Statistics/OA&M Controller (NMXSOX)
The NMXSOX implements ingress and egress OA&M
functions as specified in the ITU and Bellcore recom-
mendations.
Its main functions are OA&M cell type recognition and
validation, and implementation of fault management
defect indication, loopback, continuity check on all con-
nections, and performance monitoring for up to 127
OA&M processes.
The NMXSOX also maintains per-connection as well as
per-port and global cell event information (arriving/
departing, enqueued/dequeued cells, and related time-
stamps) which can be communicated to an external
adjunct device for connection statistics collection and
performance monitoring data collection.
Enhanced Services Interface (ESI)
NMXESI implements a 16-bit parallel interface between
the APC and an optional external adjunct device to
support value-added enhanced services. The APC
reports a rich set of events through this interface to
support the implementation of virtually any customer
desired per-connection, per-port, or per-device statistic
in the external device.
ABR Flow Control Engine (XREAFE)
The ABR flow control engine (AFE) operates on
ingress and egress ABR traffic to control switch and
network congestion. The user has the option to globally
select among different flow control algorithms imple-
mented by the AFE. These are the selective EFCI
marking algorithm and a Bell Labs’ patented algorithm.
The ABR flow control algorithm can selectively operate
on a minimum cell rate (MCR) plus equal share or pro-
portional to MCR basis.
Only one ABR flow control algorithm can be active at a
given time. The AFE also supports backward RM cell
consolidation for up to 1023 fabric port multicast con-
nections and 1023 egress subport multicast connec-
tions.
To support its operations, the AFE performs RM cell
validation and calculates queue lengths and traffic load
on subports (egress) or fabric ports (ingress).
Microprocessor Interface (MPI)
The MPI provides a generic 32-bit asynchronous
microprocessor interface with maskable interrupts. This
allows an external processor to access the APC for
configuration, maintenance, statistics, internal and
external memory reads and writes, as well as interrupt
services.
The MPI also provides high-performance DMA support
for fast cell insertion and extraction via FIFOs at the
microprocessor interface.
Global Time Counter (TCT)
The TCT generates all the signals necessary for inter-
nal event synchronization. It also generates the exter-
nal synchronization pulse GTSYNC.
Global Clock (WCK)
WCK generates all the clocks needed in the APC, as
well as the output fabric clocks.
Reset Driver (RST)
RST synchronizes an externally applied, active-low,
asynchronous reset pulse, and generates all the sig-
nals needed to reset the internal blocks of the APC.
Reset is applied synchronously on each of the internal
clock domains of the APC.
JTAG Test Access Port (JTG)
The APC incorporates logic to support a standard
5-pin test access port (TAP), compatible with the IEEE
1149.1 standard (JTAG), used for boundary scan. TAP
contains instruction registers, data registers, and con-
trol logic. It is controlled externally by a JTAG bus mas-
ter. The JTG gives the APC board-level test capability.
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相关代理商/技术参数 |
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| T-APD1126DN-R | 制造商:IDEC CORPORATION 功能描述:T-APD1126DN-R |
| T-APD199N-A-120V | 制造商:IDEC CORPORATION 功能描述:T-APD199N-A-120V |
| T-APD199N-A-24V | 制造商:IDEC CORPORATION 功能描述:T-APD199N-A-24V |
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