参数资料
型号: TAS5026CPAG
厂商: TEXAS INSTRUMENTS INC
元件分类: 消费家电
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP64
封装: PLASTIC, TQFP-64
文件页数: 20/52页
文件大小: 886K
代理商: TAS5026CPAG
Architecture Overview
22
SLES041B—November 2002
TAS5026
Read and write operations to the TAS5026 can be done using single byte or multiple byte data transfers.
2.5.1 Single Byte Write
As shown in Figure 2–14, a single byte data write transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction
of the data transfer. For a write data transfer, the read/write bit is 0. After receiving the correct I2C device
address and the read/write bit, the TAS5026 device responds with an acknowledge bit. Next, the master
transmits the address byte or bytes corresponding to the TAS5026 internal memory address being accessed.
After receiving the address byte, the TAS5026 again responds with an acknowledge bit. Next, the master
device transmits the data byte to be written to the memory address being accessed. After receiving the data
byte, the TAS5026 again responds with an acknowledge bit. Finally, the master device transmits a stop
condition to complete the single byte data write transfer.
A6
A5
A4
A3
A2
A1
A0
R/W ACK A7
A6
A5
A4
A3
A2
A1
A0
ACK
D7
D6
D5
D4
D3
D2
D1
D0
ACK
Start Condition
Stop
Condition
Acknowledge
I2C Device Address and
Read/Write Bit
Register Address
Data Byte
Figure 2–14. Single Byte Write Transfer
2.5.2 Multiple Byte Write
A multiple byte data write transfer is identical to a single byte data write transfer except that multiple data bytes
are transmitted by the master device to TAS5026 as shown in Figure 2–15. After receiving each data byte,
the TAS5026 responds with an acknowledge bit.
D7
D6
D1
D0 ACK
Stop
Condition
Acknowledge
I2C Device Address and
Read/Write Bit
Register Address
Last Data Byte
A6
A5
A1
A0
R/W ACK A7
A5
A1
A0
ACK D7
D6
D1
D0 ACK
Start Condition
Acknowledge
First Data Byte
A4
A3
A6
Other
Data Bytes
Figure 2–15. Multiple Byte Write Transfer
2.5.3 Single Byte Read
As shown in Figure 2–16, a single byte data read transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. For the data read transfer, a write followed
by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal memory
address to be read. As a result, the read/write bit is 0. After receiving the TAS5026 address and the read/write
bit, the TAS5026 responds with an acknowledge bit. Also, after sending the internal memory address byte or
bytes, the master device transmits another start condition followed by the TAS5026 address and the read/write
bit again. This time the read/write bit is a 1 indicating a read transfer. After receiving the TAS5026 and the
read/write bit, the TAS5026 again responds with an acknowledge bit. Next, the TAS5026 transmits the data
byte from the memory address being read. After receiving the data byte, the master device transmits a not
acknowledge followed by a stop condition to complete the single byte data read transfer.
A6
A5
A0 R/W ACK A7
A6
A5
A4
A0 ACK
A6
A5
A0
ACK
Start
Condition
Stop
Condition
Acknowledge
I2C Device Address and
Read/Write Bit
Register Address
Data Byte
D7
D6
D1
D0 ACK
I2C Device Address and
Read/Write Bit
Repeat Start Condition
Not
Acknowledge
R/W
A1
Figure 2–16. Single Byte Read
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