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| 型号： | TAS5026CPAG |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封装： | PLASTIC, TQFP-64 |
| 文件页数： | 3/52页 |
| 文件大小： | 886K |
| 代理商： | TAS5026CPAG |
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Architecture Overview
6
SLES041B—November 2002
TAS5026
2
Architecture Overview
The TAS5026 is composed of six functional elements:
Clock, PLL, and serial data interface (IIS)
Reset/power down circuitry
Serial control interface (IIC)
Signal processing unit
Pulse width modulator (PWM)
Power supply
2.1
Clock and Serial Data Interface
The TAS5026 clock and serial data interface contains an input serial data slave and the clock master/ slave
interface.
The serial data slave interface receives information from a digital source such as a DSP, S/PDIF receiver,
analog-to-digital converter (ADC), digital audio processor (DAP) such as the TAS3103, or other serial bus
master at sample rates of for sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz,176.4 kHz, and 192
kHz. The serial data interface has three serial data inputs that can accept up to six channels of data. The serial
data interfaces support left justified and right justified for 16-, 20-, and 24-bits. In addition, the serial data
interfaces support the DSP protocol for 16 bits and the I2S protocal for 24 bits. The received data is data
passed to the TAS5026 signal-processing unit.
The TAS5026 can function as a receiver or a generator for the MCLK_IN (master clock), SCLK (shift clock),
and LRCLK (left/right clock) signals that control the flow of data on the three serial data interfaces. The
TAS5026 is a clock master when it generates these clocks and is a clock slave when it receives these clocks.
The TAS5026 is a synchronous design that relies upon master clock to provide a reference clock for all of the
device operations. When operating as a slave, this reference clock is MCLK_IN. When operating as a master,
the reference clock is either TTL clock input to XTAL_IN or a crystal attached across XTAL_IN and XTAL_OUT.
If the master clock stops, the TAS5026 will perform a clock error recovery sequence. The clock error recovery
sequence temporarily suspends processing, places the PWM outputs in a hard mute (PWM_P outputs are
low; PWM_M outputs are high, and all VALID signals are low), resets all internal processes, sets the volumes
to mute, and suspends all I2C operations.
When the master clock is resumed, the TAS5026 exits the clock error recovery sequence by performing a
4.3-ms partial re-initialization, noiselessly restarting the PWM output, and ramping the volume up to the level
specified in the volume control registers. The volume update is performed over a 43-ms. interval. The
TAS5026 preserves all control register settings that were set prior to the clock interruption.
If a clock error occurs while the ERR_RCVRY pin is asserted (LOW), the TAS5026 will perform the error
recovery sequence up to the unmute sequence. In this case, the volume remains at full attenuation with the
PWM output at a 50% duty cycle. The volume can be restored from this state by triggering a mute/unmute
sequence via the mute pin LOW then HIGH.
The clock and serial data interface has two control parameters: data sample rate and clock master or slave.
2.1.1 Normal-Speed, Double-Speed, and Quad-Speed Selection
The sampling rate is selected through a pin (DBSPD) or the serial control register 0 (X02). When a sample
rate is selected, the system automatically performs an error recovery sequence and switches to the new
sampling rate. As shown in subsequent sections, the sample rate control sets the frequencies of the SCLK
and LRCLK in clock slave mode and the output frequencies of SCLK and LRCLK in clock master mode.
During the error recovery sequence, the TAS5026 temporarily suspends processing, places the PWM outputs
in a hard mute (PWM P outputs LOW; PWM M outputs HIGH, and all VALID signals LOW), resets all internal
processes, and suspends all I2C operations. The TAS5026 then performs a 4.3-ms partial re-initialization and
noiselessly restarts the PWM output. The TAS5026 preserves all control register settings through out the error
recovery sequence.
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| TAS5026IPAG | 功能描述:多媒体杂项 Dig Aud PWM Proc RoHS:否 制造商:Texas Instruments 类型: 通道数量: 转换速率:540 Mbps 分辨率: 封装 / 箱体:SOIC-16 封装:Tube |
| TAS5026IPAGG4 | 功能描述:多媒体杂项 Dig Aud PWM Proc RoHS:否 制造商:Texas Instruments 类型: 通道数量: 转换速率:540 Mbps 分辨率: 封装 / 箱体:SOIC-16 封装:Tube |
| TAS5026IPAGR | 功能描述:多媒体杂项 Dig Aud PWM Proc RoHS:否 制造商:Texas Instruments 类型: 通道数量: 转换速率:540 Mbps 分辨率: 封装 / 箱体:SOIC-16 封装:Tube |
| TAS5026IPAGRG4 | 功能描述:多媒体杂项 Dig Aud PWM Proc RoHS:否 制造商:Texas Instruments 类型: 通道数量: 转换速率:540 Mbps 分辨率: 封装 / 箱体:SOIC-16 封装:Tube |
| TAS5026PAG | 功能描述:多媒体杂项 Dig Aud PWM Proc RoHS:否 制造商:Texas Instruments 类型: 通道数量: 转换速率:540 Mbps 分辨率: 封装 / 箱体:SOIC-16 封装:Tube |
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