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参数资料
| 型号： | TAS5186DDVR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 音频／视频放大 |
| 英文描述： | 60 W, 6 CHANNEL, AUDIO AMPLIFIER, PDSO44 |
| 封装： | GREEN, PLASTIC, HTSSOP-44 |
| 文件页数： | 6/16页 |
| 文件大小： | 342K |
| 代理商： | TAS5186DDVR |
www.ti.com
Overtemperature Protection
UNDERVOLTAGE PROTECTION (UVP) AND
DEVICE RESET
ACTIVE-BIAS CONTROL (ABC)
TAS5186
SLES136 – MAY 2005
ABC can pre-charge the dc-blocking element in the
audio path, i.e., split-cap capacitors or series capaci-
The TAS5186 has a two-level temperature-protection
tor, to the desired potential before switching is started
system that asserts an active-low warning signal
on the PWM outputs. (For recommended configur-
(OTW) when the device junction temperature ex-
ation, see the typical application schematic included
ceeds 125°C (typical), and If the device junction
in this data sheet).
temperature exceeds 155°C (typical), the device is
put into thermal shutdown, resulting in all half-bridge
The start-up sequence can be controlled through
outputs being set in the high-impedance state (Hi-Z)
sequencing the M3 and RESET pins according to
and SD being asserted low.
Table 2. 5.1 Mode—All Output Channels Active
POWER-ON RESET (POR)
M3
RESET
OUT_BIAS
OUT_A, OUT_D,
COMMENT
_B, _C
_E, _F
The UVP and POR circuits of the TAS5186 fully
0
Hi-Z
All outputs dis-
protect
the
device
in
any
power-up/down
and
abled, nothing is
brownout situation. While powering up, the POR
switching.
circuit resets the overload circuit (OLP) and ensures
1
0
Active
Hi-Z
OUT_BIAS en-
that all circuits are fully operational when the
abled, all other
GVDD_X and VDD supply voltages reach 10 V
outputs disabled
(typical). Although GVDD_X and VDD are indepen-
1
Hi-Z
Active
OUT_BIAS dis-
dently monitored, a supply voltage drop below the
abled, all other
UVP threshold on any VDD or GVDD_X pin results in
outputs
switching
all half-bridge outputs immediately being set in the
high-impedance (Hi-Z) state and SD being asserted
low. The device automatically resumes operation
Table 3. 2.1 Mode—Only Output Channels A, B,
when all supply voltages have increased above the
and C Active
UVP threshold.
M3
RESET
OUT_BIAS
OUT_A, OUT_D,
COMMENT
_B, _C
_E, _F
0
Hi-Z
All outputs dis-
abled, nothing is
When RESET is asserted low, the output FETs in all
switching.
half-bridges are forced into a high-impedance (Hi-Z)
1
0
Active
Hi-Z
OUT_BIAS en-
state.
abled, all other
outputs disabled
Asserting the RESET input low removes any fault
information to be signaled on the SD output, i.e., SD
0
1
Hi-Z
Active
Hi-Z
OUT_BIAS dis-
abled, all other
is forced high.
outputs
A rising-edge transition on the RESET input allows
switching
the device to resume operation after an overload
When the TAS5186 is used with the TAS5086 PWM
fault.
modulator, no special attention to start-up sequencing
is required, provided that the chipset is configured as
recommended.
Audible
pop
noises
are
often
associated
with
single-rail, single-ended power stages at power-up or
at the start of switching. This commonly known
problem has been virtually eliminated by incorpor-
ating a proprietary active-bias control circuitry as part
of the TAS5186 feature set. By the use of only a few
passive external components (typically resistors), the
14
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