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参数资料
型号： TAS5508PAGR
厂商： TEXAS INSTRUMENTS INC
元件分类： 消费家电
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封装： GREEN, PLASTIC, TQFP-64
文件页数： 74/105页
文件大小： 1286K
代理商： TAS5508PAGR
TAS5508
8-Channel Digital Audio PWM Processor
SLES091D – FEBRUARY 2004 – REVISED JULY 2009
www.ti.com
TOTAL
I2C
REGISTER FIELDS
DESCRIPTION OF CONTENTS
DEFAULT STATE
BYTES
SUBADDRESS
SDIN1 – left to input mixer 1
SDIN1 – right to input mixer 2
SDIN2 – left to input mixer 3
Input mixer registers,
SDIN2 – right to input mixer 4
0x41–0x48
32/reg.
8
＝8 input crossbar mixer setup
Ch1–Ch8
SDIN3 – left to input mixer 5
SDIN3 – right to input mixer 6
SDIN4 – left to input mixer 7
SDIN4 – right to input mixer 8
0x49
4
ipmix_1_to_ch8
Input mixer 1 to Ch8 mixer coefficient
0.0
0x4A
4
ipmix_2_to_ch8
Input mixer 1 to Ch8 mixer coefficient
0.0
0x4B
4
ipmix_7_to_ch2
Input mixer 7 to Ch2 mixer coefficient
0.0
0x4C
4
Ch7_bp_bq2
Bypass Ch7 biquad 2 coefficient
0.0
0x4D
4
Ch7_bq2
Ch7 biquad 2 coefficient
1.0
0x4E
4
ipmix_8_to_ch12
Ch8 biquad 2 output to Ch1 mixer and
0.0
Ch2 mixer coefficient
0x4F
4
Ch8_bp_bq2
Bypass Ch8 biquad 2 coefficient 0
0.0
0x50
4
Ch8_bq2
Ch8 biquad 2 coefficient
1.0
0x51–0x88
20/reg.
Biquad filter register
Ch1–Ch8 biquad filter coefficients
All biquads = All pass for all channels
0x89–0x90
8
Bass and treble bypass
Bypass bass and treble for Ch1–Ch8
Bass and treble bypassed for all channels
register, Ch1–Ch8
0x91
4
Loudness Log2 LG
0.5
0x92
8
Loudness Log2 LO
0.0
0x93
4
Loudness G
0.0
0x94
8
Loudness O
0.0
Loudness biquad coefficient b0
0x00, 0x00, 0xD5, 0x13
Loudness biquad coefficient b1
0x00, 0x00, 0x00, 0x00
0x95
20
Loudness biquad
Loudness biquad coefficient b2
0x0F, 0xFF, 0x2A, 0xED
Loudness biquad coefficient a0
0x00, 0xFE, 0x50, 0x45
Loudness biquad coefficient a1
0x0F, 0x81, 0xAA, 0x27
0x96
4
DRC1 control Ch1–Ch7
DRC1 disabled in Ch1–Ch7
0x97
4
DRC2 control register, Ch8
DRC2 control Ch8
DRC2 disabled in Ch8
Ch1–Ch7, DRC1 energy
DRC1 energy
0.0041579
0x98
8
Ch1–Ch7, DRC1 (1 –
DRC1 (1 – energy)
0.9958421
energy)
Ch1–Ch7 DRC1 threshold
DRC1 threshold (T1) – upper 2 bytes
0x00, 0x00, 0x00, 0x00
T1
DRC1 threshold (T1) – lower 4 bytes
0x0B, 0x20, 0xE2, 0xB2
0x99
16
Ch1–Ch7 DRC1 threshold
DRC1 threshold (T2) – upper 2 bytes
0x00, 0x00, 0x00, 0x00
T2
DRC1 threshold (T2) – lower 4 bytes
0x06, 0xF9, 0xDE, 0x58
Ch1–Ch7 , DRC1 slope k0
DRC1 slope (k0)
0x0F, 0xC0, 0x00, 0x00
0x9A
12
Ch1–Ch7, DRC1 slope k1
DRC1 slope (k1)
0x0F, 0xC0, 0x00, 0x00
Ch1–Ch7 DRC1 slope k2
DRC1 slope (k2)
0x0F, 0x90, 0x00, 0x00
Ch1–Ch7 DRC1 offset 1
DRC1 offset 1 (O1) – upper 2 bytes
0x00, 0x00, 0xFF, 0xFF
DRC1 offset 1 (O1) – lower 4 bytes
0xFF, 0x82, 0x30, 0x98
0x9B
16
Ch1–Ch7 DRC1 offset 2
DRC1 offset 2 (O2) – upper 2 bytes
0x00, 0x00, 0x00, 0x00
DRC1 offset 2 (O2) – lower 4 bytes
0x01, 0x95, 0xB2, 0xC0
Ch1–Ch7 DRC1 attack
DRC1 attack
0x00, 0x00, 0x88, 0x3F
Ch1–Ch7 DRC1 (1 – attack)
DRC1 (1 – attack)
0x00, 0x7F, 0x77, 0xC0
0x9C
16
Ch1–Ch7 DRC1 decay
DRC1 decay
0x00, 0x00, 0x00, 0xAE
Ch1–Ch7 DRC1 (1 – decay)
DRC1 (1 – decay)
0x00, 0x7F, 0xFF, 0x51
Ch8 DRC2 energy
DRC2 energy
0x00, 0x00, 0x88, 0x3F
0x9D
8
Ch8 DRC2 (1 – energy)
DRC2 (1 – energy)
0x00, 0x7F, 0x77, 0xC0
DRC2 threshold (T1) – upper 2 bytes
0x00, 0x00, 0x00, 0x00
Ch8 DRC2 threshold T1
DRC2 threshold (T1) – lower 4 bytes
0x0B, 0x20, 0xE2, 0xB2
0x9E
16
DRC2 threshold (T2) – upper 2 bytes
0x00, 0x00, 0x00, 0x00
Ch8 DRC2 threshold T2
DRC2 threshold (T2) – lower 4 bytes
0x06, 0xF9, 0xDE, 0x58
70
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