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参数资料
型号： TAS5508PAGR
厂商： TEXAS INSTRUMENTS INC
元件分类： 消费家电
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封装： GREEN, PLASTIC, TQFP-64
文件页数： 90/105页
文件大小： 1286K
代理商： TAS5508PAGR
7.19 Bass and Treble Bypass Register, Channels 1–8 (0x89–0x90)
7.20 Loudness Registers (0x91–0x95)
7.21 DRC1 Control Registers, Channels 1–7 (0x96)
TAS5508
8-Channel Digital Audio PWM Processor
www.ti.com
SLES091D – FEBRUARY 2004 – REVISED JULY 2009
Table 7-19. Contents of One 20-Byte Biquad Filter Register (Default = All-Pass) (continued)
DEFAULT GAIN COEFFICIENT VALUES
DESCRIPTION
REGISTER FIELD CONTENTS
DECIMAL
HEX
b1 coefficient
u[31:28], b1[27:24], b1[23:16], b1[15:8], b1[7:0]
0.0
0x00, 0x00, 0x00, 0x00
b2 coefficient
u[31:28], b2[27:24], b2[23:16], b2[15:8], b2[7:0]
0.0
0x00, 0x00, 0x00, 0x00
a1 coefficient
u[31:28], a1[27:24], a1[23:16], a1[15:8], a1[7:0]
0.0
0x00, 0x00, 0x00, 0x00
a2 coefficient
u[31:28], a2[27:24], a2[23:16], a2[15:8], a2[7:0]
0.0
0x00, 0x00, 0x00, 0x00
Channels 1, 2, 3, 4, 5, 6, 7, and 8 are mapped into registers 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F,
and 0x90, respectively. Eight bytes are written for each channel. Each gain coefficient is in 28-bit (5.23)
format so 0x80 0000 is a gain of 1. Each gain coefficient is written as a 32-bit word with the upper four bits
not used.
Table 7-20. Channel 1–8 Bass and Treble Bypass Register Format
REGISTER
TOTAL
CONTENTS
INITIALIZATION VALUE
NAME
BYTES
Channel bass and
u[31:28], bypass[27:24], bypass[23:16], bypass[15:8], bypass[7:0]
0x00, 0x80, 0x00, 0x00
treble bypass
8
Channel bass and
u[31:28], inline[27:24], inline[23:16], inline[15:8], inline[7:0]
0x00, 0x00, 0x00, 0x00
treble inline
Table 7-21. Loudness Register Format
I2C SUB-
TOTAL
REGISTER NAME
DESCRIPTION OF CONTENTS
DEFAULT STATE
ADDRESS BYTES
0x91
4
Loudness Log2 gain (LG)
u[31:28], LG[27:24], LG[23:16], LG[15:8], LG[7:0]
0xFF, 0xC0, 0x00, 0x00
Loudness Log2 offset (LO)
u[31:24], u[23:16], LO[15:8], LO[7:0]
0x00, 0x00, 0x00, 0x00
0x92
8
Loudness Log2 LO
LO[31:24], LO[23:16], LO[15:8], LO[7:0]
0x00, 0x00, 0x00, 0x00
0x93
4
Loudness gain (G)
u[31:28], G[27:24], G[23:16], G[15:8], G[7:0]
0x00, 0x00, 0x00, 0x00
Loudness offset upper
u[31:24], u[23:16], O[15:8], O[7:0]
0x00, 0x00, 0x00, 0x00
16 bits (O)
0x94
8
Loudness O offset lower 32
O[31:24], O[23:16], O[15:8], O[7:0]
0x00, 0x00, 0x00, 0x00
bits (O)
Loudness biquad (b0)
u[31:28], b0[27:24], b0[23:16], b0[15:8], b0[7:0]
0x00, 0x00, 0xD5, 0x13
Loudness biquad (b1)
u[31:28], b1[27:24], b1[23:16], b1[15:8], b1[7:0]
0x00, 0x00, 0x00, 0x00
0x95
20
Loudness biquad (b2)
u[31:28], b2[27:24], b2[23:16], b2[15:8], b2[7:0]
0x0F, 0xFF, 0x2A, 0xED
Loudness biquad (a1)
u[31:28], a1[27:24], a1[23:16], a1[15:8], a1[7:0]
0x00, 0xFE, 0x50, 0x45
Loudness biquad (a2)
u[31:28], a2[27:24], a2[23:16], a2[15:8], a2[7:0]
0x0F, 0x81, 0xAA, 0x27
Bits D31–D14 are Don't Care.
Table 7-22. Channel 1–7 DCR1 Control Register Format
D31
D30
D29
D28
D27
D26
D25
D24
FUNCTION
Unused bits
D23
D22
D21
D20
D19
D18
D17
D16
FUNCTION
Unused bits
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Serial-Control Interface Register Definitions
85
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