参数资料
型号: TC1271ALCVCTTR
厂商: Microchip Technology
文件页数: 21/48页
文件大小: 0K
描述: IC RESET MONITOR 4.63V SOT23A-5
标准包装: 1
类型: 简单复位/加电复位
监视电压数目: 1
输出: 推挽式,图腾柱
复位: 高有效
复位超时: 最小为 17.5 ms
电压 - 阀值: 4.63V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: SC-74A,SOT-753
供应商设备封装: SOT-23-5
包装: 标准包装
产品目录页面: 662 (CN2011-ZH PDF)
其它名称: TC1271ALCVCTDKR
TC1270A/70AN/71A
Table 4-2 shows the various device trip point options
4.2.1
HYSTERESIS
and their V TRIP(MAX) and V TRIP(MIN) voltages. The neg-
ative percentage change from common regulated
voltages is also shown.
If the V DD is falling from the regulated voltage as it
crosses the V TRIP voltage, the RST/RST pin is driven
active. Then, the desired circuitry is forced into Reset,
or the circuitry has the indication that the V DD is below
the selected V TRIP .
If th e V DD is rising as it crosses the V TRIP voltage, the
RST/RST pin is driven inactive after the Reset Delay
Timer elapses. Then, the desired circuitry is released
from Reset and will start to operate in its Normal mode,
or the circuitry has the indication that the V DD is above
the selected V TRIP .
There is also a minimal hysteresis (V HYS ) on the trip
point. This is so that small noise signals on the device
voltage (V DD ) do not cause the Reset pin (RST/RST) to
“jitter” (oscillate between active and inactive levels).
The characterization graphs shown in Figures 2-13
through 2-15 show the device hysteresis as a
percentage of the voltage trip point (V TRIP ).
The Reset Delay Timer (t RST ) gives a time-based
hysteresis for the system.
4.2.2 POWER-UP/RISING V DD
As the device V DD rises, the device’s Reset circuit will
remain active until the voltage rises above the “actual”
trip point (V TRIP ).
TABLE 4-2:
SELECTING THE TRIP POINT
Figure 4-7 shows a power-up sequence and the
Trip
Voltage
Selection
V TRIP(MAX)( 1 ) /
V TRIP(MIN)( 2 )
- % From
Regulated Voltage
5.0V 3.3V 3.0V
waveform of the RST and RST pins. As the device
powers up, the voltage will start below the valid
operating voltage of the device. At this voltage, the
RST/RST output is not valid. Once the voltage is above
L
M
T
S
4.75V
4.50V
4.50V
4.25V
3.15V
3.00V
3.00V
2.85V
5.0%
10.0%
10.0%
15.0%
4.5%
9.2%
9.2%
13.7%
the minimum operating voltage (1V) and below the
selected V TRIP , the Reset output will be active.
Once the device voltage rises above the V TRIP voltage,
the Reset Delay Timer (t RST ) starts. When the Reset
Delay Timer times out, the Reset output (RST/RST) is
driven inactive.
V TRIP
R
2.70V
2.55V
10.0%
15.0%
V DD
1V
t RST (1)
Note 1:
Voltage regulator circuit must have tighter
tolerance (%) than V TRIP(MAX) % from
regulated voltage.
RST (2)
2:
Circuitry being reset must have a wider
tolerance (%) than V TRIP(MIN) % from
regulated voltage.
The TC1270A/TC1270AN/TC1271A devices are
optimized to reject fast transient glitches on the V DD
line. If the low input signal (which is below V TRIP ) is not
rejected, the Reset output is driven active within 50 μs
of V DD falling through the Reset voltage threshold.
After the device exits the Reset condition, the delay
circuitry will hold the RST/RST pin active until the
appropriate Reset delay time (t RST ) has elapsed.
RST
Note 1: Additional system current is consumed
during the t RST time.
2: The TC1270AN requires an external
pull-up resistor.
During device power-up, the input voltage is below the
trip point voltage. The device must enter the valid oper-
ating range for the device to start operation.
? 2007-2011 Microchip Technology Inc.
FIGURE 4-7:
Power-up.
RST/RST Pin Operation
DS22035D-page 21
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