参数资料
型号: TC55NEM216AFTN70
厂商: Toshiba Corporation
英文描述: CONNECTOR ACCESSORY
中文描述: 连接器附件
文件页数: 1/11页
文件大小: 181K
代理商: TC55NEM216AFTN70
TC55NEM216AFTN55,70
2002-07-04 1/11
TENTATIVE
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
262,144-WORD BY 16-BIT FULL CMOS STATIC RAM
DESCRIPTION
The TC55NEM216AFTN is a 4,194,304-bit static random access memory (SRAM) organized as 262,144 words by
16 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 5V
±
10% power supply. Advanced circuit technology provides both high speed and low power at an operating current of 3
mA/MHz (typ) and a minimum cycle time of 55 ns. It is automatically placed in low-power mode at 1
μ
A standby
current (typ) when chip enable (CE) is asserted high. There are two control inputs. CE is used to select the device
and for data retention control, and output enable (OE ) provides fast memory access. Data byte control pin (LB,
UB ) provides lower and upper byte access. This device is well suited to various microprocessor system applications
where high speed, low power and battery backup are required. And, with a guaranteed operating extreme
temperature range of
40° to 85°C, the TC55NEM216AFTN can be used in environments exhibiting extreme
temperature conditions. The TC55NEM216AFTN is available in a plastic 54-pin thin-small-outline package
(TSOP).
FEATURES
Low-power dissipation
Operating: 15 mW/MHz (typical)
Single power supply voltage of 5 V
±
10%
Power down features using CE
Data retention supply voltage of 2.0 to 5.5 V
Direct TTL compatibility for all inputs and outputs
Wide operating temperature range of
40° to 85°C
Standby Current (maximum): 20
μ
A
PIN ASSIGNMENT
(TOP VIEW)
54 PIN TSOP
PIN NAMES
A0~A17
Address Inputs
CE
Chip Enable
R/W
Read/Write Control
OE
Output Enable
LB ,
UB
Data Byte Control
I/O1~I/O16
Data Inputs/Outputs
V
DD
Power (
+
5 V)
GND
Ground
NC
No Connection
OP
*
Option
*
: OP pin must be open or connected to GND.
Access Times (maximum):
TC55NEM216AFTN
55
70
Access Time
55 ns
70 ns
CE
Access Time
55 ns
70 ns
OE
Access Time
30 ns
35 ns
Package:
TSOP II54-P-400-0.80
(Weight: g typ)
NC
A3
A2
A1
A0
I/O16
I/O15
V
GND
I/O14
I/O13
UB
R/W
I/O12
I/O11
GND
V
I/O10
I/O9
NC
A17
A16
A15
A14
A13
A4
A5
A6
A7
NC
I/O1
I/O2
V
GND
I/O3
I/O4
NC
I/O5
I/O6
GND
V
I/O7
I/O8
A8
A9
A10
A11
A12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
CE
OE
LB
相关PDF资料
PDF描述
TC55NEM216AFTN55 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
TC55V1001AFTI 131,072-Word By 8-Bit Static RAM(131,072字 × 8位静态RAM)
TC55V1001ASRI 131,072-Word By 8-Bit Static RAM(131,072字 × 8位静态RAM)
TC55V1001ASTI 131,072-Word By 8-Bit Static RAM(131,072字 × 8位静态RAM)
TC55V1001ATRI 131,072-Word By 8-Bit Static RAM(131,072字 × 8位静态RAM)
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