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| 型号： | TC7126RIPL |
| 元件分类： | ADC |
| 英文描述： | 1-CH DUAL-SLOPE ADC, PARALLEL ACCESS, PDIP40 |
| 封装： | REVERSE, PLASTIC, DIP-40 |
| 文件页数： | 4/26页 |
| 文件大小： | 413K |
| 代理商： | TC7126RIPL |
TC7126/A
DS21458C-page 12
2006 Microchip Technology Inc.
6.0
COMPONENT VALUE
SELECTION
6.1
Auto-Zero Capacitor (CAZ)
The CAZ capacitor size has some influence on system
noise. A 0.47
μF capacitor is recommended for 200mV
full scale applications where 1LSB is 100
μV. A 0.033μF
capacitor is adequate for 2.0V full scale applications. A
mylar type dielectric capacitor is adequate.
6.2
Reference Voltage Capacitor (CREF)
The reference voltage, used to ramp the integrator out-
put voltage back to zero during the reference integrate
phase, is stored on CREF. A 0.1μF capacitor is accept-
able when VREF- is tied to analog common. If a large
Common mode voltage exists (VREF- – analog com-
mon) and the application requires a 200mV full scale,
increase CREF to 1μF. Rollover error will be held to less
than 0.5 count. A Mylar type dielectric capacitor is
adequate.
6.3
Integrating Capacitor (CINT)
CINT should be selected to maximize integrator output
voltage swing without causing output saturation. Due to
the TC7126A’s superior analog common temperature
coefficient specification, analog common will normally
supply the differential voltage reference. For this case,
a ±2V full scale integrator output swing is satisfactory.
For 3 readings per second (FOSC = 48kHz), a 0.047μF
value is suggested. For 1 reading per second, 0.15
μF
is recommended. If a different oscillator frequency is
used, CINT must be changed in inverse proportion to
maintain the nominal ±2V integrator swing.
An exact expression for CINT is:
EQUATION 6-1:
At 3 readings per second, a 750
Ω resistor should be
placed in series with CINT. This increases accuracy by
compensating for comparator delay. CINT must have
low dielectric absorption to minimize rollover error. A
polypropylene capacitor is recommended.
6.4
Integrating Resistor (RINT)
The input buffer amplifier and integrator are designed
with Class A output stages. The output stage idling
current is 6
μA. The integrator and buffer can supply
1
μA drive current with negligible linearity errors. RINT is
chosen to remain in the output stage linear drive
region, but not so large that PC board leakage currents
induce errors. For a 200mV full scale, RINT is 180kΩ. A
2V full scale requires 1.8M
Ω.
Note:
FOSC = 48kHz (3 readings per sec).
6.5
Oscillator Components
COSC should be 50pF; ROSC is selected from the
equation:
EQUATION 6-2:
For a 48kHz clock (3 conversions per second),
R = 180k
Ω.
Note that FOSC is 44 to generate the TC7126A’s
internal clock. The backplane drive signal is derived by
dividing FOSC by 800.
To achieve maximum rejection of 60Hz noise pickup,
the signal integrate period should be a multiple of
60Hz. Oscillator frequencies of 24kHz, 12kHz, 80kHz,
60kHz, 40kHz, etc. should be selected. For 50Hz rejec-
tion,
oscillator
frequencies
of
20kHz,
100kHz,
66-2/3kHz, 50kHz, 40kHz, etc. would be suitable. Note
that 40kHz (2.5 readings per second) will reject both
50Hz and 60Hz.
CINT =
(4000)
1
FOSC
VFS
RINT
VINT
Where:
FOSC = Clock frequency at Pin 38
VFS = Full scale input voltage
RINT = Integrating resistor
VINT = Desired full scale integrator output swing
Component
Value
Nominal Full Scale Voltage
200mV
2V
CAZ
0.33
μF
0.033
μF
RINT
180k
Ω
1.8M
Ω
CINT
0.047
μF
0.047
μF
FOSC =
0.45
RC
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