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参数资料
| 型号： | TC7135CPI |
| 元件分类： | ADC |
| 英文描述： | 1-CH 9-BIT DUAL-SLOPE ADC, PARALLEL ACCESS, PDIP28 |
| 封装： | PLASTIC, DIP-28 |
| 文件页数： | 15/16页 |
| 文件大小： | 217K |
| 代理商： | TC7135CPI |
8
TC7135
4-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
TC7135-10 9/27/99
Figure 8. Strobe Signal Pulses Low Five Times per Conversion
Figure 7. Timing Diagrams for Outputs
The active-low STROBE pulses aid BCD data transfer
to UARTs, microprocessors, and external latches. (See
Application Note AN-16.)
BUSY Output
At the beginning of the signal-integration phase, BUSY
(pin 21) goes high and remains high until the first clock pulse
after the integrator zero crossing. BUSY returns to logic "0"
after the measurement cycle ends in an overrange condi-
tion. The internal display latches are loaded during the first
clock pulse after BUSY and are latched at the clock pulse
end. The BUSY signal does not go high at the beginning of
the measurement cycle, which starts with the auto-zero
phase.
OVERRANGE Output
If the input signal causes the reference voltage integra-
tion time to exceed 20,000 clock pulses, the OVERRANGE
output (pin 27) is set to logic "1." The OVERRANGE output
register is set when BUSY goes low and reset at the
beginning of the next reference-integration phase.
UNDERRANGE Output
If the output count is 9% of full scale or less (
≤1800
counts), the UNDERRANGE output (pin 28) register bit is
set at the end of BUSY. The bit is set low at the next signal-
integration phase.
STROBE Output
During the measurement cycle, the STROBE output
(pin 26) control line is pulsed low five times. The five low
pulses occur in the center of the digit drive signals (D1, D2,
D3, D4 and D5; see Figure 8).
D5 goes high for 201 counts when the measurement
cycles end. In the center of D5 pulse, 101 clock pulses after
the end of the measurement cycle, the first STROBE occurs
for one-half clock pulse. After D5 strobe, D4 goes high for 200
clock pulses. STROBE goes low 100 clock pulses after D4
goes high. This continues through the D1 drive pulse.
The digit drive signals will continue to permit display
scanning. STROBE pulses are not repeated until a new
measurement is completed. The digit drive signals will not
continue if the previous signal resulted in an overrange
condition.
,
,
INTEGRATOR
OUTPUT
OVERRANGE
WHEN
APPLICABLE
UNDERRANGE
WHEN
APPLICABLE
SYSTEM
ZERO
10,001
COUNTS
SIGNAL
INTE
10,000
COUNTS
(FIXED)
REFERENCE
INTEGRATE
20,001
COUNTS (MAX)
FULL MEASUREMENT CYCLE
40,002 COUNTS
BUSY
EXPANDED SCALE
BELOW
D5
D4
D3
D2
D1
100
COUNTS
DIGIT SCAN
STROBE
AUTO ZERO
SIGNAL
INTEGRATE
REFERENCE
INTEGRATE
D5
D4
D3
D2
D1
DIGIT SCAN
FOR
OVERRANGE
FIRST D5 OF SYSTEM ZERO
AND REFERENCE INTEGRATE
ONE COUNT LONGER.
*
END OF CONVERSION
D5 (MSD)
DATA
BUSY
B1–B8
STROBE
D5
D4
D3
D2
D1
D4
DATA
D3
DATA
D2
DATA
D1 (LSD)
DATA
D5
DATA
NOTE ABSENCE
OF STROBE
201
COUNTS
200
COUNTS
200
COUNTS
200
COUNTS
200
COUNTS
200
COUNTS
200
COUNTS
*
*DELAY BETWEEN BUSY GOING LOW AND FIRST STROBE
PULSE IS DEPENDENT ON ANALOG INPUT.
TC7135
OUTPUTS
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相关代理商/技术参数 |
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|---|---|
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