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参数资料
| 型号： | TC820CLW |
| 元件分类： | ADC |
| 英文描述： | 1-CH DUAL-SLOPE ADC, PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 8/28页 |
| 文件大小： | 616K |
| 代理商： | TC820CLW |
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TC820
DS21476B-page 16
2002 Microchip Technology Inc.
4.2.1
EOC/HOLD
EOC/HOLD is a dual purpose, bi-directional pin. As an
output, this pin goes low for 10 clock cycles at the end
of each conversion. This pulse latches the conversion
data into the display driver section of the TC820.
EOC/HOLD can be used to hold (or "FREEZE") the dis-
play. Connecting this pin to VDD inhibits the display
update process. Conversions will continue, but the dis-
play will not change. EOC/HOLD will hold the display
reading for either analog-to-digital, or frequency
measurements.
The input/output structure of the EOC/HOLD pin is
shown in Figure 4-1. The output drive current is only a
few microAmps, so EOC/HOLD can easily be over-
driven by an open collector logic gate, as well as a FET,
bipolar transistor, or mechanical switch. When used as
an output, EOC/HOLD will have a slow rise and fall
time due to the limited output current drive. A CMOS
Schmitt trigger buffer is recommended.
FIGURE 4-1:
EOC/HOLD PIN
4.2.2
OVER RANGE (OR),
UNDER RANGE (UR)
The OR output will be high when the analog input sig-
nal is greater than full scale (3999 counts). The UR out-
put will be high when the display reading is 380 counts
or less.
The OR and UR outputs can be used to provide an
auto-ranging meter function. By logically ANDing these
outputs with the inverted EOC/HOLD output, a single
pulse will be generated each time an under ranged or
over ranged conversion occurs (Figure 4-2).
FIGURE 4-2:
GENERATING UNDER
RANGE AND OVER
RANGE PULSES
4.2.3
VDISP
The VDISP input sets the peak-to-peak LCD drive volt-
age. In the 40-pin package, VDISP is connected inter-
nally to DGND, providing a typical LCD drive voltage of
5VP-P. The 44-pin package includes a separate VDISP
input for applications requiring a variable or tempera-
ture compensated LCD drive voltage. See the applica-
tions information for suggested circuits.
4
EOC/HOLD
Display
Update
EOC
TC820
≈ 500k
EOC/HOLD
TC820
UR
OR
*74HC132
*
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| TC820CPL | 1-CH DUAL-SLOPE ADC, PDIP40 |
| TC820CLW | DUAL-SLOPE ADC, PARALLEL ACCESS, PQCC44 |
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| TC821CKW | CONVERTER SUBSYSTEM ADC, PARALLEL ACCESS, PQFP44 |
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