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| 型号： | TC9404FNG |
| 元件分类： | DAC |
| 英文描述： | PARALLEL, WORD INPUT LOADING, 1-BIT DAC, PDSO24 |
| 封装： | 0.300 INCH, 0.65 MM PITCH, PLASTIC, SSOP-24 |
| 文件页数： | 10/15页 |
| 文件大小： | 369K |
| 代理商： | TC9404FNG |
TC9404FNG
2006-04-27
4
Description of Block Operations
1.
Crystal Oscillator Circuit and Timing Generator
The clock required for internal operations is generated by connecting a crystal and condensers as shown
in the diagram below.
The IC will also operate when a system clock is input from an external source through the XI pin (pin 15).
However, in this situation, due consideration must be given to the fact that waveform characteristics, such
as jitter and rising/falling characteristics of the system clock, significantly affect the DA converter’s noise
distortion and the S/N ratio.
CL = 10~33 pF
Use a crystal with a low CI value and favorable start-up characteristics.
The timing generator generates the clocks and process timing signals required for such functions as
digital filtering and de-emphasis filtering.
2.
Data Input Circuit
DATA and the LRCK are loaded to the LSI internal shift registers on the BCK signal rising edge. It is
consequently necessary for the DATA and LRCK signals to be synchronized and input on the BCK signal
falling edge as indicated in the timing example below. Also, as DATA has been designed so that the 16 bits
before the change point of LRCK are regarded as valid data, the data must be input with Right-justified
mode when the BCK is 48 fs or 64 fs, as shown in Figure 2b.
Figure 1
Crystal Oscillation Circuit Configuration (when in the 384 fs mode)
Figure 2a
Example of Input Timing Chart
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