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| 型号： | TC9404FNG |
| 元件分类： | DAC |
| 英文描述： | PARALLEL, WORD INPUT LOADING, 1-BIT DAC, PDSO24 |
| 封装： | 0.300 INCH, 0.65 MM PITCH, PLASTIC, SSOP-24 |
| 文件页数： | 12/15页 |
| 文件大小： | 369K |
| 代理商： | TC9404FNG |
TC9404FNG
2006-04-27
6
4.
De-Emphasis Filter
The built-in digital de-emphasis circuit is available for three kind of sampling frequency, fs of 32 kHz,
44.1 kHz, and 48 kHz. These setting controlled in the parallel mode ( S
P/ = “H”) with the LATCH (BS) pin
(pin 18) and SHIFT (EMP) pin (pin 19).
This is set in the serial mode ( S
P/ = “L”) with a microcontroller or other equipment. (refer to 9-2
microcontroller setting mode for further details on serial mode settings.)
Table 2
De-Emphasis Filter Setting (when in the parallel mode)
LATCH (BS)
H
L
SHIFT (EMP)
H
L
H
L
MODE (fs SELECT)
32
48
44.1
OFF
(kHz)
The digitalization of the de-emphasis filter eliminates the need for such external components as resistors,
condensers and analog switches. In addition to this, the coefficients are aligned to reduce error in the
de-emphasis filter characteristics.
The filter structure and characteristics are shown below.
Transfer function:
)
Z
a
(1
)
Z
b
(
(Z)
H
1
0
+
=
T1 = 50 s, T2 = 15 s
5.
DA Conversion Circuit
The IC incorporates a 2’nd Σ- modulation DA converter for two channels (simultaneous output type).
The internal structure of this is shown in Figure 6.
2’nd
∑- converter: Y (Z) = X (Z) + (1 Z1)2Q (Z)
Figure 4
IIR Digital De-Emphasis Filter
Figure 5
Filter Characteristics
Figure 6
Σ- Modulation DA Converter
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