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参数资料
| 型号： | TC9404FNG |
| 元件分类： | DAC |
| 英文描述： | PARALLEL, WORD INPUT LOADING, 1-BIT DAC, PDSO24 |
| 封装： | 0.300 INCH, 0.65 MM PITCH, PLASTIC, SSOP-24 |
| 文件页数： | 15/15页 |
| 文件大小： | 369K |
| 代理商： | TC9404FNG |
TC9404FNG
2006-04-27
9
9-2
Serial Mode (
S
P/
= “L”: microcontroller setting mode)
It is possible to make the various settings with a microcontroller when in the serial mode.
Pins 18, 19 and 20 are used as the command input pins shown in the table below when in the serial
mode.
Table 4
Pin Names at The Serial Mode
Pin No.
Pin Name
Function
18
LATCH
Data latch signal input pin
19
SHIFT
Shift clock signal input pin
20
ATT
Data input pin
The LATCH signals and ATT signals are loaded to the LSI internal shift registers on the SHIFT
signal rising edge. It is consequently necessary for the data input from the ATT pin on the shift signal
rising edge to be valid as indicated in the timing example in Figure 10. It is also necessary for the
LATCH pulse to rise at least 1.5 s after the final clock rising edge input from the SHIFT pin.
Operating the shift clock with LATCH low destabilizes the internal state, which may lead to
malfunctions, so it must therefore be set to the low level after loading D7 to the register.
A
= 1.5 s or higher, B = 1.5 s or higher
The various control settings when in the serial mode are shown in the table below.
Ensure that all control bits are set when the power supply is turned on.
Table 5
Serial Mode Control Settings
Serial Input Data
Control Signal
D7
0
1
D6
AT6
BS
D5
AT5
EMP
D4
AT4
D3
AT3
D2
AT2
D1
AT1
D0
AT0
AT0~6: Attenuation level setting
BS: De-emphasis mode select
EMP: De-emphasis ON/OFF switch
Figure 10
Example of Data Setting Timing in the Serial Mode
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