TCM4400E
GSM/DCS BASEBAND AND VOICE A/D
AND D/A RF INTERFACE CIRCUIT
SLWS082A – JULY 1999 – REVISED MARCH 2000
19
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
MCU serial interface timing requirements (see Figure 3)
PARAMETER
MIN
NOM
MAX
UNIT
tsu10
tv1
tv2
th9
th10
th11
tsu11
th12
tc
Setup time, UCLK stable before USEL
↓
Hold time, UDX valid after USEL
↓
Hold time, UDX valid after UCLK
↑
Sequential transfer delay between 16-bit word acquisition tw pulse duration, USEL high
Hold time, UCLK
↑
after USEL
↓
Hold time, UCLK unknown after USEL
↑
Setup time, data valid before UCLK
↓
Hold time, data valid after UCLK
↓
Cycle time, ULCK
20
ns
20
ns
20
ns
3000
ns
20
ns
20
ns
20
ns
20
ns
154
ns
DSP serial interface timing requirements (see Figure 4)
PARAMETER
MIN
NOM
MAX
UNIT
BCLKX
BCLKX signal frequency ( Burst mode or Continuous mode depending on bit BCLKMODE)
13
MHz
BCLKX
BCLKX duty cycle
Setup time, BFSX high before BCLKX
↓
Hold time, BFSX high after BCLKX
↓
Setup time, BDX valid before BCLKX
↓
Hold time, BDX valid after BCLKX
↓
40%
50%
60%
tsu12
th12
tsu13
th13
20
ns
20
ns
20
ns
20
ns
BCLKR
BCLKR signal frequency
(Output BCLKDIR = 0)
4.33
MHz
(Input BCLKDIR = 1)
13
BCLKR
BCLKR duty cycle
Setup time, BFSR high before BCLKR
↓
Hold time, BFSR high after BCLKR
↓
Setup time, BDR valid before BCLKR
↓
Setup time, BDR valid after BCLKR
↓
40%
50%
60%
tsu14
th14
tsu16
th15
20
ns
20
ns
20
ns
20
ns
voice timing requirements (see Figure 5)
PARAMETER
MIN
NOM
MAX
UNIT
VCLK
VCLK signal frequency ( Burst mode or Continuous mode depending on bit VCLKMODE)
520
kHz
VCLK
VCLK duty cycle
Setup time, VFS high before VCLK
↓
Hold time, VFS high after VCLK
↓
Setup time, VDX valid before VCLK
↓
Hold time, VDX valid after VCLK
↓
Setup time, VDR valid before VCLK
↓
40%
50%
60%
tsu7
th6
tsu8
th8
tsu9
th7
100
ns
100
ns
100
ns
100
ns
100
ns
Hold time, VDR valid after VCLK
↓
100
ns