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| 型号： | TCM4400ETQFP |
| 厂商： | Texas Instruments, Inc. |
| 英文描述： | GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT |
| 中文描述： | 的GSM / DCS的基带和语音的A / D和D / A射频接口电路 |
| 文件页数： | 23/64页 |
| 文件大小： | 888K |
| 代理商： | TCM4400ETQFP |
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TCM4400E
GSM/DCS BASEBAND AND VOICE A/D
AND D/A RF INTERFACE CIRCUIT
SLWS082A – JULY 1999 – REVISED MARCH 2000
23
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
DSP serial port timing considerations
Figure 4 shows the timing diagram for DSP serial port operation.
Six pins are used for the serial port interface; see Figure 14. The terminal BCLKR is an I/O port for the serial
clock used to control the reception of the data BDR. At reset BCLKR is configured as an output and the clock
frequency is set to MCLK/3 (4.333 MHz with MCLK = 13 MHz); the clock signal is running permanently. The port
BCLKR can be reconfigured as an input by programming an internal register. In this case BCLKR is provided
by the DSP and can run in burst mode to reduce power consumption. The receive frame synchronization (BFSR)
identifies the beginning of a data packet transfer on port BDR.
The transmitted serial data (BDX) is the serial data input; the transmit frame synchronization (BFSX) is used
to initiate the transmission of data. The transmit clock (BCLKX) is provided by the GSM baseband and voice
A/D and D/A converters with a frequency of MCLK. The downlink data bus (BFSX, BCLKX, BDX) can be driven
to VSS or placed in high-impedance when no data is to be transferred to the DSP. The bit BCLKDIR of the
register BCTLREG controls the direction of the BCLKR clock.
Similar to the voice serial interface, an extra clock cycle must be generated, since the last 16-bit word received
on the DSP serial interface is latched on the next two falling BCLKR edges, following the least significant bit
(LSB). As for the voice serial interface, one extra clock period is generated on the BCLKX before the first
synchronization BFSX of downlink data sequence.
BCLKX
tsu12
th13
tsu13
th14
BFSX
BDX
A15
A14
A13
A12
A3
A2
A1
A0
MSB
LSB
a. Burst-Mode Serial-Port Transmit Operation
tsu14
th14
tsu15
th15
BDR
A15
A14
A13
A12
A3
A2
A1
A0
MSB
LSB
b. Burst-Mode Serial-Port Receive Operation
B15
B14
B13
BCLKR
BFSR
Figure 4. DSP Serial Port Timings
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