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参数资料
| 型号： | TDA1310AT-T |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 0.2 us SETTLING TIME, 16-BIT DAC, PDSO8 |
| 封装： | PLASTIC, SOT-96AG, SO-8 |
| 文件页数： | 12/16页 |
| 文件大小： | 114K |
| 代理商： | TDA1310AT-T |
May 1994
5
Philips Semiconductors
Preliminary specication
Stereo Continuous Calibration DAC
(CC-DAC)
TDA1310A
PINNING
SYMBOL
PIN
DESCRIPTION
BCK
1
bit clock input
WS
2
word select input
DATA
3
data input
GND
4
ground
VDD
5
supply voltage
IOL
6
left channel output
Iref
7
reference input
IOR
8
right channel output
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION
The basic operation of the continuous calibration DAC is
illustrated in Fig.3. The figure shows the calibration and
operation cycle. During calibration of the MOS current
source (Fig.3a) transistor M1 is connected as a diode by
applying a reference current. The voltage Vgs on the
intrinsic gate-source capacitance Cgs of M1 is then
determined by the transistor characteristics. After
calibration of the drain current to the reference value Iref,
the switch S1 is opened and S2 is switched to the other
position (Fig.3b). The gate-to-source voltage Vgs of M1 is
not changed because the charge on Cgs is preserved.
Therefore, the drain current of M1 will still be equal to Iref
and this exact duplicate of Iref is now available at the OUT
terminal.
The 32 current sources and the spare current source of the
TDA1310A are continuously calibrated (see Fig.1). The
spare current source is included to allow continuous
converter operation. The output of one calibrated source is
connected to an 11-bit binary current divider consisting of
2048 transistors. A symmetrical offset decoding principle
is incorporated and arranges the bit switching in such a
way that the zero-crossing is performed only by switching
the LSB currents.
The TDA1310A (CC-DAC) accepts serial input data
formats of 16-bit word length. Left and right data words are
time multiplexed. The most significant bit (bit 1) must
always be first. The input data format is shown in
Figs 4 and 5.
With a HIGH level on the word select input (WS), data is
placed in the left input register, with a LOW level on the
WS input, data is placed in the right input register
(see Fig.1). The data in the input registers are
simultaneously latched in the output registers which
control the bit switches.
An internal bias current Ibias is added to the full scale
output current IFS in order to achieve the maximum
dynamic range at the outputs OP1 and OP2 in Fig.1.
The reference input current Iref controls with gain GFS, the
current IFS which is a sink current and with gain Gbias the
Ibias which is a source current(1).
The current Iref is proportional to VDD so the IFS and the Ibias
will be proportional to VDD as well(2) because GFS and Gbias
are constant.
The reference voltage Vref in Fig.1 is 23VDD. In this way
maximum dynamic range is achieved over the entire
power supply voltage range.
The tolerance of the reference input current in Fig.1
depends on the tolerance of the resistors R3, R4
and Rref(3).
(1) IFS =GFS xIref and Ibias =Gbias xIref
(2)
(3)
V
DD1
V
DD2
-------------
I
FS1
I
FS2
----------
I
bias1
I
bias2
--------------
==
I
ref
I
ref
V
DD
R3
R3 R4 R4 R
ref
R
ref
++
+
-------------------------------------------------------------------------------------------------
–
=
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