- 您现在的位置：买卖IC网 > PDF目录85415 > TDA4853/V2 (NXP SEMICONDUCTORS) HORIZ/VERT DEFLECTION IC, PDIP32 PDF资料下载
参数资料
| 型号： | TDA4853/V2 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 偏转 |
| 英文描述： | HORIZ/VERT DEFLECTION IC, PDIP32 |
| 封装： | PLASTIC, SDIP-32 |
| 文件页数： | 2/63页 |
| 文件大小： | 318K |
| 代理商： | TDA4853/V2 |
第1页当前第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页
1999 Jul 13
10
Philips Semiconductors
Product specication
I2C-bus autosync deection controllers for
PC/TV monitors
TDA4853; TDA4854
PLL2 phase detector
The PLL2 phase detector is similar to the PLL1 detector
and compares the line flyback pulse at HFLB (pin 1) with
the oscillator sawtooth voltage. The control currents are
independent of the horizontal frequency. The PLL2
detector thus compensates for the delay in the external
horizontal deflection circuit by adjusting the phase of the
HDRV (pin 8) output pulse.
For the TDA4854 external modulation of the PLL2 phase
is not allowed, because this would disturb the start
advance of the horizontal focus parabola.
Soft start and standby
If HPLL2 is pulled to ground by resetting the
register SOFTST, the horizontal output pulses, vertical
output currents and B+ control driver pulses will be
inhibited. This means that HDRV (pin 8), BDRV (pin 6),
VOUT1 (pin 13) and VOUT2 (pin 12) are floating in this
state. If HPLL2 is pulled to ground by an external DC
current, vertical output currents stay active while HDRV
(pin 8) and BDRV (pin 6) are in floating state. In both cases
the PLL2 and the frequency-locked loop are disabled,
CLBL (pin 16) provides a continuous blanking signal and
HUNLOCK (pin 17) is floating.
This option can be used for soft start, protection and
power-down modes. When the HPLL2 pin is released
again, an automatic soft start sequence on the horizontal
drive as well as on the B+ drive output will be performed
(see Figs 26 and 27).
A soft start can only be performed if the supply voltage for
the IC is a minimum of 8.6 V.
The soft start timing is determined by the filter capacitor at
HPLL2 (pin 30), which is charged with a constant current
during soft start. If the voltage at pin 30 (HPLL2) reaches
1.1 V, the vertical output currents are enabled. At 1.7 V the
horizontal driver stage generates very small output pulses.
The width of these pulses increases with the voltage at
HPLL2 until the final duty cycle is reached. The voltage at
HPLL2 increases further and performs a soft start at BDRV
(pin 6) as well. The voltage at HPLL2 continues to rise until
HPLL2 enters its normal operating range. The internal
charge current is now disabled. Finally PLL2 and the
frequency-locked loop are activated. If both functions
reach normal operation, HUNLOCK (pin 17) switches from
the floating status to normal vertical blanking, and
continuous blanking at CLBL (pin 16) is removed.
Output stage for line drive pulses [HDRV (pin 8)]
An open-collector output stage allows direct drive of an
inverting driver transistor because of a low saturation
voltage of 0.3 V at 20 mA. To protect the line deflection
transistor, the output stage is disabled (floating) for a low
supply voltage at VCC (see Fig.25).
The duty cycle of line drive pulses is slightly dependent on
the actual horizontal frequency. This ensures optimum
drive conditions over the whole frequency range.
X-ray protection
The X-ray protection input XRAY (pin 2) provides a voltage
detector with a precise threshold. If the input voltage at
XRAY exceeds this threshold for a certain time then
control bit SOFTST is reset, which switches the IC into
protection mode. In this mode several pins are forced into
defined states:
HUNLOCK (pin 17) is floating
The capacitor connected to HPLL2 (pin 30) is
discharged
Horizontal output stage (HDRV) is floating
B+ control driver stage (BDRV) is floating
Vertical output stages (VOUT1 and VOUT2) are floating
CLBL provides a continuous blanking signal.
There are two different methods of restarting the IC:
1. XSEL (pin 9) is open-circuit or connected to ground.
The control bit SOFTST must be set to logic 1 via the
I2C-bus. The IC then returns to normal operation via
soft start.
2. XSEL (pin 9) is connected to VCC via an external
resistor. The supply voltage of the IC must be switched
off for a certain period of time before the IC can be
restarted again using the standard power-on
procedure.
相关PDF资料 |
PDF描述 |
|---|---|
| TDA4853NB | HORIZ/VERT DEFLECTION IC, PDIP32 |
| TDA2616/N1 | 15 W, 2 CHANNEL, AUDIO AMPLIFIER, PSIP9 |
| TDA2616Q/N1 | 15 W, 2 CHANNEL, AUDIO AMPLIFIER, PSIP9 |
| TDA6101Q/N3 | 1 CHANNEL, VIDEO AMPLIFIER, PZFM9 |
| TDA6101QU | 1 CHANNEL, VIDEO AMPLIFIER, PZFM9 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TDA4854 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:I2C-bus autosync deflection controllers for PC/TV monitors |
| TDA4855 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Autosync Deflection Controller ASDC |
| TDA4856 | 制造商:Phil 功能描述:Semiconductor |
| TDA4857 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:I2C-bus autosync deflection controller for PC monitors |
| TDA4857PS | 制造商:NXP Semiconductors 功能描述:HORIZ/VERT DEFLECTION IC, PDIP32 |
发布紧急采购，3分钟左右您将得到回复。