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| 型号： | TDA9115 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 偏转 |
| 英文描述： | HORIZ/VERT DEFLECTION IC, PDIP32 |
| 封装： | SHRINK, PLASTIC, DIP-32 |
| 文件页数： | 19/45页 |
| 文件大小： | 675K |
| 代理商： | TDA9115 |
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TDA9115
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9.3.3 Voltage controlled oscillator
The VCO makes part of both PLL1 and PLL2
loops, being an “output” to PLL1 and “input” to
PLL2. It delivers a linear sawtooth. Figure 6 ex-
plains its principle of operation. The linears are ob-
tained by charging and discharging an external ca-
pacitor on pin CO, with currents proportional to the
current forced through an external resistor on pin
RO, which itself depends on the input tuning volt-
age VHO (filtered charge pump output). The rising
and falling linears are limited by VHOThrLo and
VHOThrHi thresholds filtered through HOscF pin.
At no signal condition, the VHO tuning voltage is
clamped to its minimum (see chapter ELECTRI-
CAL PARAMETERS AND OPERATING CONDI-
TIONS, part horizontal section), which corre-
sponds to the free-running VCO frequency fHO(0).
Refer to Note1 for the formula to calculate this fre-
quency using external components values. The ra-
tio between the frequency corresponding to maxi-
mum VHO and the one corresponding to minimum
VHO (free-running frequency) is about 4.5. This
range can easily be increased in the application.
The PLL1 can only lock to input frequencies falling
inside these two limits.
9.3.4 PLL2
The goal of the PLL2 is, by means of phasing the
signal driving the power deflection transistor, to
lock the middle of the horizontal flyback to a cer-
tain threshold of the VCO sawtooth. This internal
threshold is affected by geometry phase correc-
tions, like e.g., parallelogram. The PLL2 is much
faster than PLL1 to be able to follow the dynamism
of this phase modulation. The PLL2 control current
(see Figure 7) is significantly increased during dis-
charge of vertical oscillator (during vertical retrace
period) to be able to make up for the difference of
dynamic phase at the bottom and at the top of the
picture. The PLL2 control current is integrated on
the external filter on pin HPLL2C to obtain
smoothed voltage, used, in comparison with VCO
ramp, as a threshold for H-drive rising edge gener-
ation.
As both leading and trailing edges of the H-drive
signal in the Figure 7 must fall inside the rising part
of the VCO ramp, an optimum middle position of
the threshold has been found to provide enough
margin for horizontal output transistor storage time
as well as for the trailing edge of H-drive signal
with maximum duty cycle. Yet, the constraints
thereof must be taken into account while consider-
ing the application frequency range and H-flyback
duration. The Figure 7 also shows regions for ris-
ing and falling edges of the H-drive signal on HOut
pin. As it is forced high during the H-flyback pulse
and low during the VCO discharge period, no edge
during these two events takes effect.
The flyback input configuration is in Figure 8.
9.3.5 Dynamic PLL2 phase control
The dynamic phase control of PLL2 is used to
compensate for picture asymmetry versus vertical
axis across the middle of the picture. It is done by
modulating the phase of the horizontal deflection
with respect to the incoming video (synchroniza-
tion). Inside the device, the threshold VS(0) is com-
pared with the VCO ramp, the PLL2 locking the
middle of H-flyback to the moment of their match.
The dynamic phase is obtained by modulation of
the threshold by correction waveforms. Refer to
Figure 12 and to chapter TYPICAL OUTPUT
WAVEFORMS. The correction waveforms have
no effect in vertical middle of the screen (for mid-
dle vertical position). As they are summed, their ef-
fect on the phase tends to reach maximum span at
top and bottom of the picture. As all the compo-
nents of the resulting correction waveform (linear
for parallelogram correction and parabola of 2nd
order for Pin cushion asymmetry correction) are
generated from the output vertical deflection drive
waveform, they both track with real vertical ampli-
tude and position (including breathing compensa-
tion), thus being fixed on the screen. Refer to I2C
BUS CONTROL REGISTER MAP on page 20 for
details on I2C bus controls.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| TDA9116 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:LOW-COST I2C CONTROLLED DEFLECTION PROCESSOR FOR MULTISYNC MONITOR |
| TDA9118 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:行/场扫描处理电路 |
| TDA9141 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:PAL/NTSC/SECAM decoder/sync processor |
| TDA9143 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor |
| TDA9144 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator |
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