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参数资料
| 型号： | TDA9115 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 偏转 |
| 英文描述： | HORIZ/VERT DEFLECTION IC, PDIP32 |
| 封装： | SHRINK, PLASTIC, DIP-32 |
| 文件页数： | 21/45页 |
| 文件大小： | 675K |
| 代理商： | TDA9115 |
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TDA9115
28/45
Figure 10. Control of HOut and BOut at start/stop at nominal Vcc
9.4 VERTICAL SECTION
9.4.1 General
The goal of the vertical section is to drive vertical
deflection output stage. It delivers a sawtooth
waveform with an amplitude independent of de-
flection frequency, on which vertical geometry cor-
rections of C- and S-type are superimposed (see
chapter TYPICAL OUTPUT WAVEFORMS).
Block diagram is in Figure 11. The sawtooth is ob-
tained by charging an external capacitor on pin
VCap with controlled current and by discharging it
via transistor Q1. This is controlled by the CON-
TROLLER. The charging starts when the voltage
across the capacitor drops below VVOB threshold.
The discharging starts either when it exceeds VVOT
threshold or a short time after arrival of synchroni-
zation pulse. This time is necessary for the AGC
loop to sample the voltage at the top of the saw-
tooth. The VVOB reference is routed out onto VO-
scF pin in order to allow for further filtration.
The charging current influences amplitude and
shape of the sawtooth. Just before the discharge,
the voltage across the capacitor on pin VCap is
sampled and stored on a storage capacitor con-
nected on pin VAGCCap. During the following ver-
tical period, this voltage is compared to internal
reference REF (VVOT), the result thereof control-
ling the gain of the transconductance amplifier pro-
viding the charging current. Speed of this AGC
loop depends on the storage capacitance on pin
VAGCCap. On the screen, this corresponds to sta-
bilized vertical size of picture. After a change of
frequency on the sync. input, the stabilization time
depends on the frequency difference and on the
capacitor value. The lower its value, the shorter
the stabilization time, but on the other hand, the
lower the loop stability. A practical compromise is
a capacitance of 470nF. The leakage current of
this capacitor results in difference in amplitude be-
tween low and high frequencies. The higher its
parallel resistance RL(VAGCCap), the lower this dif-
ference.
When the synchronization pulse is not present, the
charging current is fixed. As a consequence, the
free-running frequency fVO(0) only depends on the
value of the capacitor on pin VCap. It can be
roughly calculated using the following formula
fVO(0) =
The frequency range in which the AGC loop can
regulate the amplitude also depends on this ca-
pacitor.
The C- and S-corrections of shape serve to com-
pensate for the vertical deflection system non-line-
arity. They are controlled via
CCOR and SCOR
I2C bus controls.
Shape-corrected sawtooth with regulated ampli-
tude is lead to amplitude control stage. The dis-
t
V(HPosF)
Soft start
Soft stop
Normal operation
Start
HOut
Start
BOut
Stop
HOut
Stop
BOut
HOut
H-duty cycle
BOut (positive)
B-duty cycle
100%
0%
VHOn
VBOn
VHBNorm
VHPosMax
VHPosMin
HPOS (I2C)
range
minimum value
maximum value
C(VCap)
. 100Hz
150nF
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相关代理商/技术参数 |
参数描述 |
|---|---|
| TDA9116 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:LOW-COST I2C CONTROLLED DEFLECTION PROCESSOR FOR MULTISYNC MONITOR |
| TDA9118 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:行/场扫描处理电路 |
| TDA9141 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:PAL/NTSC/SECAM decoder/sync processor |
| TDA9143 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor |
| TDA9144 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator |
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