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参数资料
型号： TE28F016B3T150
厂商： INTEL CORP
元件分类： DRAM
英文描述： SMART 3 ADVANCED BOOT BLOCK BYTE-WIDE
中文描述： 2M X 8 FLASH 3V PROM, 150 ns, PDSO40
封装： 10 X 20 MM, TSOP-40
文件页数： 14/49页
文件大小： 408K
代理商： TE28F016B3T150
SMART 3 ADVANCED BOOT BLOCK
–BYTE-WIDE
E
14
PRELIMINARY
3.0
PRINCIPLES OF OPERATION
Flash memory combines EEPROM functionality
with in-circuit electrical program and erase
capability. The Smart 3 Advanced Boot Block flash
memory family utilizes a Command User Interface
(CUI) and automated algorithms to simplify program
and erase operations. The CUI allows for 100%
CMOS-level control inputs, fixed power supplies
during erasure and programming, and maximum
EEPROM compatibility.
When V
PP
< V
PPLK
, the device will only execute the
following commands successfully: Read Array,
Read Status Register, Clear Status Register and
Read Intelligent Identifier. The device provides
standard EEPROM read, standby and output
disable operations. Manufacturer identification and
device identification data can be accessed through
the CUI. In addition, 2.7V or 12V on V
PP
allows
program and erase of the device. All functions
associated with altering memory contents, namely
program and erase, are accessible via the CUI.
The internal Write State Machine (WSM) completely
automates program and erase operations while the
CUI signals the start of an operation and the status
register reports status. The CUI handles the WE#
interface to the data and address latches, as well
as system status requests during WSM operation.
3.1
Bus Operation
Smart 3 Advanced Boot Block flash memory
devices read, program and erase in-system via the
local CPU or microcontroller. All bus cycles to or
from the flash memory conform to standard
microcontroller bus cycles. Four control pins dictate
the data flow in and out of the flash component:
CE#, OE#, WE# and RP#. These bus operations
are summarized in Table 3.
Table 3. Bus Operations for Byte-Wide Mode
Mode
Notes
RP#
CE#
OE#
WE#
WP#
A
0
V
PP
DQ
0
–7
Read
1,2,3
V
IH
V
IL
V
IL
V
IH
X
X
X
D
OUT
Output Disable
2
V
IH
V
IL
V
IH
V
IH
X
X
X
High Z
Standby
2
V
IH
V
IH
X
X
X
X
X
High Z
Deep Power-Down
2,9
V
IL
X
X
X
X
X
X
High Z
Intelligent Identifier (Mfr.)
2,4
V
IH
V
IL
V
IL
V
IH
X
V
IL
X
89 H
Intelligent Identifier (Dvc.)
2,4,5
V
IH
V
IL
V
IL
V
IH
X
V
IH
X
See Table 5
Write
2,6,7,
8
V
IH
V
IL
V
IH
V
IL
X
X
V
PPH
D
IN
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Refer to DC Characteristics.
X must be V
IL
, V
IH
for control pins and addresses, V
PPLK
, V
PPH1
or V
PPH2
for V
PP
.
See DC Characteristics for V
PPLK
, V
PPH1
, V
PPH2
voltages.
Manufacturer and device codes may also be accessed via a CUI write sequence, A
1
–A
20
= X
See Table 5 for device IDs.
Refer to Table 6 for valid D
IN
during a write operation.
Command writes for block erase or byte program are only executed when V
PP
= V
PPH1
or V
PPH2
.
To program or erase the lockable blocks, hold WP# at V
IH
. See Section 3.3.
RP# must be at GND
±
0.2V to meet the maximum deep power-down current specified.
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