参数资料
型号: TE28F016B3T150
厂商: INTEL CORP
元件分类: DRAM
英文描述: SMART 3 ADVANCED BOOT BLOCK BYTE-WIDE
中文描述: 2M X 8 FLASH 3V PROM, 150 ns, PDSO40
封装: 10 X 20 MM, TSOP-40
文件页数: 5/49页
文件大小: 408K
代理商: TE28F016B3T150
E
1.0
SMART 3 ADVANCED BOOT BLOCK
–BYTE-WIDE
5
PRELIMINARY
INTRODUCTION
This
specifications for the Advanced Boot Block flash
memory family, which is optimized for low power,
portable systems. This family of products features
1.8V
–2.2V or 2.V–3.6V I/Os and a low V
CC
/V
PP
operating range of 2.7V–3.6V for read and
program/erase operations. In addition this family is
capable of fast programming at 12V. Throughout
this document, the term “2.7V” refers to the full
voltage range 2.7V–3.6V (except where noted
otherwise) and “V
PP
= 12V” refers to 12V ±5%.
Section 1 and 2 provides an overview of the flash
memory family including applications, pinouts and
pin descriptions. Section 3 describes the memory
organization and operation for these products.
Finally, Sections 4, 5, 6 and 7 contain the
operating specifications.
preliminary
datasheet
contains
the
1.1
Smart 3 Advanced Boot Block
Flash Memory Enhancements
The new 8-Mbit and 16-Mbit Smart 3 Advanced
Boot Block flash memory provides a convenient
upgrade from and/or compatibility to previous 4-
Mbit and 8-Mbit Boot Block products. The Smart 3
product functions are similar to lower density
products in both command sets and operation,
providing similar pinouts to ease density upgrades.
The Smart 3 Advanced Boot Block flash memory
features
Enhanced blocking for easy segmentation of
code and data or additional design flexibility
Program Suspend command which permits
program suspend to read
WP# pin to lock and unlock the upper two (or
lower two, depending on location) 8-Kbyte
blocks
V
CCQ
input for 1.8V–2.2V on all I/Os. See
Figures 1–3 for pinout diagrams and V
CCQ
location
Maximum program time specification for
improved data storage.
Table 1. Smart 3 Advanced Boot Block Feature Summary
Feature
28F016B3/28F008B3/28F004B3
Reference
V
CC
Read Voltage
V
CCQ
I/O Voltage
V
PP
Program/Erase Voltage
Bus Width
2.7V– 3.6V
Table 9, Table 12
1.8V–2.2V or 2.7V– 3.6V
Table 9, Table 12
2.7V– 3.6V or 11.4V– 12.6V
Table 9, Table 12
8 bits
Table 2
Speed
120 ns
Table 15
Memory Arrangement
1 Mbit x 8 (8 Mbit), 2 Mbit x 8 (16 Mbit)
Blocking (top or bottom)
Eight 8-Kbyte parameter blocks (8/16 Mbit) &
Fifteen 64-Kbyte blocks (8 Mbit)
Thirty-one 64-Kbyte main blocks (16 Mbit)
Section 2.2
Figures 4 and 5
Locking
WP# locks/unlocks parameter blocks
All other blocks protected using V
PP
switch
Extended: –40
°
C to +85
°
C
10,000 cycles
40-Lead TSOP, 48-Ball
μ
BGA* CSP
Section 3.3
Table 8
Operating Temperature
Table 9, Table 12
Program/Erase Cycling
Table 9, Table 12
Packages
Figures 1, 2, and 3
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