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参数资料
| 型号： | TE28F016B3T150 |
| 厂商： | INTEL CORP |
| 元件分类： | DRAM |
| 英文描述： | SMART 3 ADVANCED BOOT BLOCK BYTE-WIDE |
| 中文描述： | 2M X 8 FLASH 3V PROM, 150 ns, PDSO40 |
| 封装： | 10 X 20 MM, TSOP-40 |
| 文件页数： | 37/49页 |
| 文件大小： | 408K |
| 代理商： | TE28F016B3T150 |
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E
SMART 3 ADVANCED BOOT BLOCK
–BYTE-WIDE
37
PRELIMINARY
Table 13. DC Characteristics: V
CCQ
= 1.8V
–2.2V
(Continued)
Sym
Parameter
Notes
V
CC1
:
2.7V–2.85V
V
CC2
:
2.7V–3.3V
Unit
Test Conditions
Typ
Max
V
IL
Input Low Voltage
–0.2
V
CCQ
–
0.2V
–0.10
0.2
V
V
IH
Input High Voltage
V
V
OL
Output Low Voltage
0.10
V
V
CC
= V
CC
Min
V
CCQ
= V
CCQ
Min
I
OL
= 100
μ
A
V
CC
= V
CC
Min
V
CCQ
= V
CCQ
Min
I
OH
= –100
μ
A
Complete Write Protection
V
OH
Output High Voltage
V
CCQ
–
0.1V
V
V
PPLK
V
PP
Lock-Out Voltage
V
PP
during Prog./Erase
Operations
3
1.5
V
V
PPH1
3
2.7
2.85
V
V
PPH2
3
2.7
3.3
V
V
PPH3
3,6
11.4
12.6
V
V
LKO1
V
CC
Program/Erase Lock
Voltage
V
CCQ
Program/Erase
Lock Voltage
1.5
V
V
LKO2
1.2
V
NOTES:
1.
2.
All currents are in RMS unless otherwise noted. Typical values at nominal V
CC
, T
A
= +25°C.
I
and I
are specified with device de-selected. If device is read while in erase suspend, current draw is I
CCR
. If the
device is read while in program suspend, current draw is I
CCR
.
Erases and Writes inhibited when V
PP
< V
PPLK
, and not guaranteed outside the valid V
PP
ranges of V
PPH1
,V
PPH2
. or V
PPH3.
Sampled, not 100% tested.
Automatic Power Savings (APS) reduces I
CCR
to approximately standby levels in static operation (CMOS inputs).
Applying V
= 11.4V–12.6V during program/erase can only be done for a maximum of 1000 cycles on the main blocks
and 2500 cycles on the parameter blocks. V
PP
may be connected to 12V for a total of 80 hours maximum. See Section 3.4
for details.
Includes the sum of V
CC
and V
CCQ
current
3.
4.
5.
6.
7
Table 14. Capacitance (T
A
= 25°C, f = 1 MHz)
Sym
Parameter
Notes
Typ
Max
Units
Conditions
C
IN
Input Capacitance
1
6
8
pF
V
IN
= 0V
C
OUT
Output Capacitance
1
10
12
pF
V
OUT
= 0V
NOTE:
1.
Sampled, not 100% tested.
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