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参数资料
| 型号： | TEA5760UK/N1/S21,1 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA25 |
| 封装： | 3 X 2.80 MM, 0.60 MM HEIGHT, WLCSP-25 |
| 文件页数： | 10/37页 |
| 文件大小： | 209K |
| 代理商： | TEA5760UK/N1/S21,1 |
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TEA5760UK_1
NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 14 December 2006
17 of 36
NXP Semiconductors
TEA5760UK
Single chip FM stereo radio
The data becomes valid byte-wise at the appropriate falling edge of the SCL clock.
A STOP condition after any byte can shorten transmission times. When writing to the
receiver by using the STOP condition before completion of the whole transfer:
– The remaining bytes will contain the old information.
– If the transfer of a byte is not completed the new bits will be used, but a new tuning
cycle will not be started.
I2C-bus activity:
With bit PUPD the TEA5760UK can be switched in a low current Standby mode. The
I2C-bus is then still active.
When the I2C-bus interface is de activated, by making pin BUSENABLE LOW and
without programmed Standby mode, the TEA5760UK keeps its normal operation, but
is isolated from the I2C-bus lines.
Bus trafc can be started 10
s after activating the bus again by making
pin BUSENABLE HIGH.
tf = fall time of both SDA and SCL signals: 20 + 0.1 Cb < tf < 300 ns, where Cb = total capacitance on bus line in pF.
tr = rise time of both SDA and SCL signals: 20 + 0.1 Cb < tr < 300 ns, where Cb = total capacitance on bus line in pF.
tHD;STA = hold time (repeated) START condition. After this period, the rst clock pulse is generated: > 600 ns.
tHIGH = HIGH period of the SCL clock: > 600 ns.
tSU;STA = set-up time for a repeated START condition: > 600 ns.
tHD;DAT = data hold time: 300 < tHD;DAT < 900 ns.
Remark: 300 ns lower limit is added because the ASIC has no internal hold time for the SDA signal.
tSU;DAT = data set-up time: tSU;DAT > 100 ns. If ASIC is used in a standard mode I2C-bus system, tSU;DAT > 250 ns.
tSU;STO = set-up time for STOP condition: > 600 ns.
tBUF = bus free time between a STOP and a START condition: > 600 ns.
Cb = capacitive load of one bus line: < 400 pF.
tsu(BUSEN) = set-up time on pin BUSEN: tsu(BUSEN) > 10 s.
th(BUSEN) = hold time on pin BUSEN: th(BUSEN) > 10 s.
Fig 9.
Bus timing diagram
P
S
Sr
P
001aaf518
tHD;STA
tBUF
tSU;STA
tSU;DAT
tf
tHIGH
tLOW
tSU;STO
tr
tHD;DAT
SDA
SCL
BUSEN
tsu(BUSEN)
th(BUSEN)
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