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参数资料
| 型号： | TEA5760UK/N1/S21,1 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA25 |
| 封装： | 3 X 2.80 MM, 0.60 MM HEIGHT, WLCSP-25 |
| 文件页数： | 6/37页 |
| 文件大小： | 209K |
| 代理商： | TEA5760UK/N1/S21,1 |
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TEA5760UK_1
NXP
B
.V
.2006.
All
r
ights
reser
v
ed.
Pr
oduct
data
sheet
Re
v
.01
—
14
December
2006
13
of
36
NXP
Semiconductor
s
TEA5760UK
Single
c
hip
FM
stereo
radio
(1) Interrupt events that occur outside of the region A-B set their respective ag bits in the normal way immediately and can thus trigger a hardware interrupt if the mask
bits are set.
(2) The blocking of interrupts is marked by the region A-B1 / B2 depending on the actual read cycle.
B1 is when only the INTFLAG is read and a stop condition is received (only INTFLAG is read so only this will be cleared).
B2 is when both registers are read and hence cleared and this is terminated by either an acknowledge or stop bit.
(3) Interrupt events that occur between A and B set their respective ags after the mask bits are cleared. Which means that in this diagram an interrupt event occurred in
period A-B, so after A-B the ag goes to logic 1.
(4) All interrupt mask bits are cleared after the interrupt ag and mask bytes are read.
(5) Software writes to the mask byte and enables the required mask bits. Any ags currently set will then trigger a hardware interrupt.
(6) INTX is set HIGH (inactive) after the interrupt mask bytes are read.
Fig 5.
I2C-bus interrupt sequence, read and write operation
001aab464
device
address
INTFLAG
INTMSK
read access
data
INTMSK
FRQSETMSB
FRQSETLSB
write access
SR
ack
interrupt event
interrupt flag bit
0R data
ack
A
(1)
(2)
(3)
interrupt mask bit
(4)
(5)
(6)
(5)
B1
B2
1R data
ack
data
ack
device
address
S
P
W
ack
0W data
ack
1W data
ack
2W data
ack
INTX
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