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参数资料
| 型号： | TEA5766UK/N1/S21,0 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 接收器 |
| 英文描述： | FM, AUDIO SINGLE CHIP RECEIVER, PBGA25 |
| 封装： | 3.30 X 3.25 MM, 0.60 MM HEIGHT, WLCSP-25 |
| 文件页数： | 28/59页 |
| 文件大小： | 273K |
| 代理商： | TEA5766UK/N1/S21,0 |
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TEA5766UK_1
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 22 March 2007
34 of 59
NXP Semiconductors
TEA5766UK
Stereo FM radio + RDS
10.3 SPI-bus
SPI stands for serial peripheral interface. TEA5766UK uses the SPI-bus in 3-wire mode,
the data-in and data-out are combined to one bidirectional data line.
For this application the SPI-bus works as a slave receiver or a slave transmitter. During an
SPI transfer, the input serial clock line SPICLK is driven by the master microcontroller up
to a frequency of 2.5 MHz and synchronizes shifting and sampling the information on the
serial data line. The slave select line CS allows individual selection of a slave SPI device.
The lines of the SPI-bus interface are associated to pins as shown in Table 11.
The TEA5766UK functions as a slave receiver and slave transmitter with a maximum
clock frequency of 2.5 MHz. Data transfer is possible when signal CS (pin BUSEN) is
LOW. When pin BUSEN is HIGH, the clock input line is disabled internally and the serial
output of the TEA5766UK is in 3-state. The data transfer consists of packages of 8 bits
data. First the address byte is shifted in, followed by 2 data bytes, which gives a total of
24 bits.
The address byte consists of 2 null bits, 5 address bits and 1 bit (R/W) for the direction of
the data transfer. The 2 null bits are added to the address byte because of the SPI 8-bit
data transfer protocol. Bits A[4:0] are the register address. All register addresses between
0 and 15 are allowed. Register addresses between 16 and 31 are not recognized and the
SPI-bus interface leaves the data line in 3-state.
The R/W bit determines the direction of the data transfer. If R/W = 1, the slave device is
set to read mode and if R/W = 0, the slave device is set to write mode.
Bits D[15:0] are the data bits. This data size corresponds to that of the register bank
implemented in the TEA5766UK. The data transfer is such that the MSB is shifted rst
and the LSB last.
When pin BUSEN becomes LOW, an SPI start condition is detected and data is sampled
in the slave device on the rising edge of the pin CLOCK signal. After the R/W bit is shifted
in, the R/W selection becomes active at the next falling edge. If R/W = 1 data will be put at
the data output and shifted out on the falling edge of the CLOCK.
When pin BUSEN becomes HIGH, the slave device (TEA5766UK) will be set to Idle
mode, in which the data output line is set to 3-state. A negative edge on pin BUSEN
Table 11.
SPI-bus control signals and pinning
SPI signal
TEA5766UK pin
Description
CS
BUSEN
chip select (active LOW)
SPICLK
CLOCK
clock input line
MOSI/MISO
DATA
serial data input and output of slave
Fig 17. SPI-bus transfer
001aaf462
D0
D15
R/W
A0
A1
A2
A3
A4
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