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| 型号： | THS1041IPWRG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封装： | GREEN, PLASTIC, TSSOP-28 |
| 文件页数： | 15/41页 |
| 文件大小： | 810K |
| 代理商： | THS1041IPWRG4 |
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THS1041
SLAS289C OCTOBER 2001 REVISED OCTOBER 2004
22
www.ti.com
PRINCIPLES OF OPERATION
onboard reference generator configuration (continued)
_
+
VBG
ADC
References
Buffer A2
MODE =
REFSENSE
AGND
VREF = External
AVDD
_
+
AVDD
2
or AVDD
Figure 33. Drive VREF Mode
operating configuration examples
Figure 34 shows a configuration using the internal ADC references for digitizing a single-ended signal with span
0 V to 2 V. Tying REFSENSE to ground gives 1 V at pin VREF. Tying MODE to AVDD/2 then sets the REFT and
REFB voltages via the internal reference generator for a 2-Vp-p ADC input range and the CLAMPOUT pin also
provides the midscale 1-V bias for the AIN input. Using the clamp to drive AIN rather than connecting AIN
directly to VREF helps to prevent kickback from the AIN pin corrupting VREF. AIN can be connected to VREF,
provided that VREF is well-decoupled to analog ground. Internal PGA gain setting is 1.
AIN+
AIN
VREF = 1 V
REFB
MODE
REFSENSE
AVDD/2
2 V
0 V
1 V
CLAMPOUT
REFT
CLAMPIN
CLAMP
AVDD
20
20
10
F
0.1
F
0.1
F
10
F 0.1 F
20 pF
1
F
Figure 34. Operating Configuration: 2-V Single-Ended Input, Internal ADC References
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