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参数资料
| 型号： | THS1041IPWRG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封装： | GREEN, PLASTIC, TSSOP-28 |
| 文件页数： | 26/41页 |
| 文件大小： | 810K |
| 代理商： | THS1041IPWRG4 |
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THS1041
SLAS289C OCTOBER 2001 REVISED OCTOBER 2004
32
www.ti.com
APPLICATION INFORMATION
steady-state clamp voltage error (continued)
V
COS
VDROOP = VAIN
tc
td
V(Clamp)
VAIN
VM
Figure 47. Approximate Waveforms at AIN During Droop and Clamping
The voltage change at AIN during acquisition has been approximated as a linear charging ramp by assuming
that almost all of VCOS appears across RIN, giving a charging current VCOS/RIN (this is a reasonable
approximation when VCOS is large enough to be of concern). The voltage change at AIN during clamp
acquisition is then:
DV
AIN +
V
COS
t
d
R
IN
C
IN
The peak-to-peak voltage variation at AIN must equal the clamp droop voltage at steady state. Equating the
droop voltage to the clamp acquisition voltage change gives:
V
COS +
R
IN
I
IN
t
d
tc
Thus for low offset voltage, keep RIN low, design for low droop and ensure that the ratio td/tc is not unreasonably
large.
reference decoupling
VREF pin
When the on-chip reference generator is enabled, the VREF pin should be decoupled to the circuit board’s
analog ground plane close to the THS1041 AGND pin via a 1-
F capacitor and a 0.1-F ceramic capacitor.
REFT and REFB pins
In any mode of operation, the REFT and REFB pins should be decoupled as shown in Figure 48. Use short
board traces between the THS1041 and the capacitors to minimize parasitic inductance.
THS1041
REFT
REFB
0.1
F
10
F
0.1
F
0.1
F
Figure 48. Recommended Decoupling for the ADC Reference Pins REFT and REFB
(19)
(20)
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