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参数资料
| 型号： | THS1240IPHP |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | ADC |
| 英文描述： | 1-CH 12-BIT DELTA-SIGMA ADC, PARALLEL ACCESS, PQFP48 |
| 封装： | POWER, PLASTIC, TQFP-48 |
| 文件页数： | 14/20页 |
| 文件大小： | 450K |
| 代理商： | THS1240IPHP |
THS1240
12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS279D – JUNE 2000 – REVISED JANUARY 2001
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
functional description
The THS1240 uses a differential pipeline architecture and assures no missing codes over the full operating
temperature range. The device uses a 1 bit per stage architecture in order to achieve the highest possible
bandwidth. The differential analog inputs are terminated with a 1-k
resistor. The inputs are then fed to a unity
gain buffer followed by the S/H (sample and hold) stage. This S/H stage is a switched capacitor operational
amplifier-based circuit, see Figure 3. The pipeline is a typical 1 bit per stage pipeline as shown in the functional
block diagram. The digital output of the 12 stages is sent to a digital correction logic block which then outputs
the final 12 bits.
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range: AVDD
– 0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DVDD
– 0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DRVDD
– 0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage between AVSS and DVSS and DRVSS
– 0.3 V to 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage between DRVDD and DVDD
– 0.5 V to 5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage between AVDD and DVDD
– 0.5 V to 5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital data output
– 0.3 V to DVDD+0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CLK peak input current, Ip(CLK)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak total input current (all inputs), Ip
– 30 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: THS1240C
0
°C to 70°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
THS1240I
– 40
°C to 85°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range
– 65
°C to 150°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds
260
°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN
NOM
MAX
UNIT
Sample rate
1
40
MSPS
Analog supply voltage, AVDD
4.75
5
5.25
V
Digital supply voltage, DVDD
4.75
5
5.25
V
Digital output driver supply voltage, DRVDD
3
3.3
5.25
V
CLK + high level input voltage, VIH
3.5
5
5.25
V
CLK + low-level input voltage, VIL
0
1.5
V
CLK pulse-width high, tp(H)
10
12.5
ns
CLK pulse-width low, tp(L)
10
12.5
ns
Operating free air temperature range TA
THS1240C
0
70
°C
Operating free-air temperature range, TA
THS1240I
– 40
85
°C
CLK– Input tied to ground with 0.01
F capacitor for single-ended clock source.
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