2–3
See Table 2-3
See Table 2-3
See Table 2-3
See Table 2-3
7.20 kHz for RB = 60
8.00 kHz for RB = 54
9.60 kHz for RB = 45
14.4 kHz for RB = 30
16.0 kHz for RB = 27
24.0 kHz for RB = 18
7.20 kHz for TB = 60
8.00 kHz for TB = 54
9.60 kHz for TB = 45
14.4 kHz for TB = 30
16.0 kHz for TB = 27
24.0 kHz for TB = 18
Divide By 2
XTAL
OSC
20.736 MHZ
41.472 MHZ
TA Register
(5 Bits)
Divide By 2
864 kHz
TB Register
(6 Bits)
RA Register
(5 Bits)
864 kHz
Divide By 4
1.296 MHz
2.592 MHz
5.184 MHz
10.368 MHz
MASTER CLOCK
TMS320 DSP
SHIFT CLOCK
TA
′
REGISTER
(6 Bits)
2s-Complement TA
See Table 2-3
Adder/Subtractor
D1 D0 SELECT
0
0
1
1
1
See Table 2-2
0
1
0
TA
TA + TA
′
TA – TA
′
TA
TX (A) Counter
(6 Bits)
TX (B) Counter
432 kHz
SCF CLOCK
Low-Pass Filter,
(sin x)/x Filter
D/A Conversion
Frequency
RA
′
Register
(6 Bits)
2s-Complement RA
See Table 2-3
Adder/Subtractor
RX (A) Counter
(6 Bits)
D1 D0 SELECT
0
0
1
1
1
See Table 2-2
0
1
0
RA
RA + RA
′
RA – RA
′
RA
RB Register
(6 Bits)
RX (B) Counter
High-Pass Filter,
A/D Conversion
Frequency
432 kHz
Low-Pass Filter
SCF CLOCK
6
12
6
12
Transmit Section
D/A Conversion
Timing
Receive Section
A/D Conversion
Timing
These control bits are described in the DX Serial Data Word Format section.
NOTES: A. Tables 2–2 and 2–3 (pages 2–9 and 2–10) are primary and secondary communication protocols,
respectively.
B. In synchronous operation, RA, RA’, RB, RX(A), and RX(B) are not used. TA, TA’, TB, TX(A), and TX(B) are
used instead.
C. Items in italics refer only to frequencies and register contents, which are variable. A crystal oscillator driving
20.736 MHz into the TMS320-series DSP provides a master clock frequency of 5.184 MHz. The TLC32047
produces a shift clock frequency of 1.296 MHz. If the TX(A) register contents equal 6, the SCF clock
frequency is then 432 kHz, and the D/A conversion frequency is 432 kHz
÷
T(B).
Figure 2–1. Asynchronous Internal Timing Configuration