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参数资料
| 型号： | TLC32047I |
| 厂商： | Texas Instruments, Inc. |
| 英文描述： | Wide-Band Analog Interface Circuit |
| 中文描述： | 宽带模拟接口电路 |
| 文件页数： | 23/61页 |
| 文件大小： | 303K |
| 代理商： | TLC32047I |
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2–5
2.7
Fundamental performance specifications for the transmit channel DAC circuitry are on pages 3-3 and 3-4.
The DAC has a sample-and-hold function that is realized with a switched-capacitor ladder.
D/A Converter
2.8
The serial port has four possible configurations summarized in the function table on page 1-2. These
configurations are briefly described below.
Serial Port
The transmit and receive sections are operated asynchronously, and the serial port interfaces
directly with the TMS320C17. The communications protocol is two 8-bit bytes.
The transmit and receive sections are operated asynchronously, and the serial port interfaces
directly with the TMS32020, TMS320C25, and TMS320C30. The communications protocol is
one 16-bit word.
The transmit and receive sections are operated synchronously, and the serial port interfaces
directly with the TMS320C17. The communications protocol is two 8-bit bytes.
The transmit and receive sections are operated synchronously, and the serial port interfaces
directly with the TMS32020, TMS320C25, TMS320C30, or two SN74299 serial-to-parallel shift
registers, which can interface in parallel to the TMS32010, TMS320C15, to any other digital
signal processor, or to external FIFO circuitry. The communications protocol is one 16-bit word.
2.9
When the transmit and receive sections are operated synchronously, the low-pass filter clock drives both
low-pass and band-pass filters (see Functional Block Diagram). The A/D conversion timing is derived from
and equal to the D/A conversion timing. When data bit D5 in the control register is a logic 1, transmit and
receive sections are synchronous. The band-pass switched-capacitor filter and the A/D converter timing are
derived from the TX(A) counter, the TX(B) counter, and the TA and TA’ registers. In synchronous operation,
both the A/D and the D/A channels operate from the same frequencies. The FSX and the FSR timing is
identical during primary communication, but FSR is not asserted during secondary communication because
there is no new A/D conversion result.
Synchronous Operation
2.9.1
The serial port interfaces directly with the serial ports of the TMS32020, TMS320C25, and the TMS320C30,
and communicates in one 16-bit word. The operation sequence is as follows:
One 16-Bit Word [Dual-Word (Telephone Interface) or Word Mode]
1.
2.
3.
4.
FSX and FSR are brought low by the TLC32047 AIC.
One 16-bit word is transmitted and one 16-bit word is received.
FSX and FSR are brought high.
EODX and EODR emit low-going pulses one shift clock wide. EODX and EODR are valid in the
word or byte mode only.
If the device is in the dual-word (telephone interface) mode, FSD goes low during the secondary
communication period and enables the data word received at the DATA-DR/CONTROL input to be routed
to the DR line. The secondary communication period occurs four shift clocks after completion of primary
communications.
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